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krx:005930
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Samsung
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Apr 26th, 2022 12:00AM
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Feb 23rd, 2021 12:00AM
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https://www.uspto.gov?id=US11315708-20220426
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Chip resistor
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A chip resistor includes: an insulating substrate; a resistor portion disposed on one surface of the insulating substrate and including a plurality of resistor bodies spaced apart from each other and a plurality of internal electrodes connecting the plurality of resistor bodies to each other; and a first external electrode and a second external electrode disposed on the one surface of the insulating substrate to be spaced apart from each other and respectively connected to the resistor portion, wherein each of the plurality of resistor bodies has a first end adjacent to the first external electrode and a second end opposing the first end and adjacent to the second external electrode, and each of the first end and the second end of each of the plurality of resistor bodies is connected to one of the plurality of internal electrodes, the first external electrode, or the second external electrode.
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11315708
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1. A chip resistor comprising:
an insulating substrate;
a resistor portion disposed on one surface of the insulating substrate, and including a plurality of resistor bodies spaced apart from each other in a width direction and a plurality of internal electrodes connecting the plurality of resistor bodies to each other; and
a first external electrode and a second external electrode disposed on the one surface of the insulating substrate to be spaced apart from each other in a length direction perpendicular to the width direction and respectively connected to the resistor portion,
wherein each of the plurality of resistor bodies has a first end adjacent to the first external electrode and a second end opposing the first end and adjacent to the second external electrode,
each of the first end and the second end of each of the plurality of resistor bodies is connected to one of the plurality of internal electrodes, the first external electrode, or the second external electrode,
at least one of the plurality of resistor bodies has a groove, and
the groove extends from an edge, the edge extending in the length direction, of the at least one of the plurality of resistor bodies inwardly of the resistor body in the width direction.
2. The chip resistor of claim 1, wherein each of the first end and the second end of each of the plurality of resistor bodies is covered with one of the plurality of internal electrodes, the first external electrode, or the second external electrode.
3. The chip resistor of claim 1, wherein the plurality of internal electrodes include a same material as that of at least one of the first external electrode or the second external electrode.
4. The chip resistor of claim 1, wherein the plurality of resistor bodies are spaced apart from each other in a width direction perpendicular to a length direction in which the first end and the second end of each of the plurality of resistor bodies oppose to each other.
5. The chip resistor of claim 4, wherein the plurality of resistor bodies include a first resistor body and a second resistor body disposed at outermost sides in the width direction,
the first resistor body is connected to the first external electrode, and
the second resistor body is connected to the second external electrode.
6. The chip resistor of claim 5, wherein the first end and the second end of each of the plurality of resistor bodies, excluding the first resistor body and the second resistor body, are connected to the plurality of internal electrodes.
7. The chip resistor of claim 1, further comprising a protective layer disposed on the resistor portion.
8. The chip resistor of claim 7, wherein the groove extends to penetrate through the protective layer.
9. The chip resistor of claim 1, further comprising a first cover electrode and a second cover electrode disposed on end portions of the insulating substrate to be spaced apart from each other and connected to the first external electrode and the second external electrode, respectively.
10. The chip resistor of claim 9, wherein each of the first and second cover electrodes includes an extending portion extending along the one surface of the insulating substrate,
a portion of the first external electrode is disposed between the insulating substrate and the extending portion of the first cover electrode, and
a portion of the second external electrode is disposed between the insulating substrate and the extending portion of the second cover electrode.
11. The chip resistor of claim 9, further comprising a protective layer disposed on the resistor portion,
wherein the protective layer entirely covers the plurality of resistor portions and the plurality of internal electrodes, and
the protective layer partially covers parts of the insulating substrate and parts of the first and second external electrodes.
12. The chip resistor of claim 11, wherein the protective layer does not cover regions of the first and second external electrodes respectively connected to the first and second cover electrodes.
13. The chip resistor of claim 11, wherein each of the first and second cover electrodes includes an extending portion extending along the one surface of the insulating substrate, and
the protective layer is in contact with one side surface of the extending portion of each of the first and second cover electrodes.
14. A chip resistor comprising:
an insulating substrate;
a resistor portion disposed on one surface of the insulating substrate, and including a plurality of resistor bodies spaced apart from each other and a plurality of internal electrodes connecting the plurality of resistor bodies to each other; and
a first external electrode and a second external electrode disposed on the one surface of the insulating substrate to be spaced apart from each other and respectively connected to the resistor portion,
wherein each of the plurality of internal electrodes covers parts of the plurality of resistor bodies,
each of the plurality of internal electrodes connects adjacent resistor bodies to each other, and
each of the plurality of internal electrodes has a portion extending along side surfaces of the adjacent resistor bodies perpendicular to the one surface of the insulating substrate.
15. The chip resistor of claim 14, wherein each of the plurality of internal electrodes covers end portions of the plurality of resistor bodies.
16. The chip resistor of claim 14, wherein at least one of the plurality of resistor bodies has a groove, and the groove extends from an edge of the at least one of the plurality of resistor bodies inwardly of the resistor body.
17. The chip resistor of claim 14, wherein each of the plurality of internal electrodes extends from the portion extending along the side surface of the internal electrodes and is bent to cover the parts of the plurality of resistor bodies.
18. A chip resistor comprising:
an insulating substrate;
a resistor portion disposed on one surface of the insulating substrate, and including a plurality of resistor bodies spaced apart from each other in a width direction and a plurality of internal electrodes each connecting adjacent resistor bodies of the plurality of resistor bodies to each other; and
a first external electrode and a second external electrode disposed on the one surface of the insulating substrate and connected to two outermost resistor bodies of the plurality of resistor bodies, respectively, in a length direction perpendicular to the width direction,
wherein the first external electrode and the second external electrode extend in opposite directions, parallel to the length direction, from respective ends of the two outermost resistor bodies, and further extend in opposite directions, parallel to the width direction, along opposing edges of the insulating substrate, such that the first external electrode and the second external electrode overlap the plurality of internal electrodes in the length direction.
19. The chip resistor of claim 18, wherein each of the plurality of internal electrodes and each of the first and second external electrodes overlap the plurality of resistor bodies in a thickness direction, perpendicular to the width and length directions.
20. The chip resistor of claim 18, wherein the plurality of internal electrodes include a same material as that of at least one of the first external electrode or the second external electrode.
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20
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CROSS-REFERENCE TO RELATED APPLICATION(S)
The present application claims the benefit of priority to Korean Patent Application No. 10-2020-0163919, filed on Nov. 30, 2020 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
TECHNICAL FIELD
The present disclosure relates to a chip resistor.
BACKGROUND
In accordance with the miniaturization and implementation of high functionality in an electronic device, a technology for a chip resistor has also been developed in line with the trend for high power, high precision, ultra-low resistance, and microminiaturization. Meanwhile, in a high-power product for realizing higher power in a chip having the same size, there is a case in which a serpentine cut is formed in a resistor body through a laser trimming process in order to improve power characteristics. In this case, there is a problem that heat may be generated due to concentration of a current on the resistor body disposed in a trimming end region.
SUMMARY
An aspect of the present disclosure may provide a chip resistor having excellent heat dissipation properties and resistance to thermal shock.
Another aspect of the present disclosure may provide a chip resistor having improved electrical characteristics.
According to an aspect of the present disclosure, a chip resistor may include: an insulating substrate; a resistor portion disposed on one surface of the insulating substrate, and including a plurality of resistor bodies spaced apart from each other and a plurality of internal electrodes connecting the plurality of resistor bodies to each other; and a first external electrode and a second external electrode disposed on the one surface of the insulating substrate to be spaced apart from each other and respectively connected to the resistor portion, wherein each of the plurality of resistor bodies has a first end adjacent to the first external electrode and a second end opposing the first end and adjacent to the second external electrode, and each of the first end and the second end of each of the plurality of resistor bodies is connected to one of the plurality of internal electrodes, the first external electrode, or the second external electrode.
According to another aspect of the present disclosure, a chip resistor may include: an insulating substrate; an insulating substrate; a resistor portion disposed on one surface of the insulating substrate, and including a plurality of resistor bodies spaced apart from each other and a plurality of internal electrodes connecting the plurality of resistor bodies to each other; and a first external electrode and a second external electrode disposed on the one surface of the insulating substrate to be spaced apart from each other and respectively connected to the resistor portion, wherein each of the plurality of internal electrodes covers parts of the plurality of resistor bodies.
According to still another aspect of the present disclosure, a chip resistor may include: an insulating substrate; a resistor portion disposed on one surface of the insulating substrate, and including a plurality of resistor bodies spaced apart from each other in a width direction and a plurality of internal electrodes each connecting adjacent resistor bodies of the plurality of resistor bodies to each other; and a first external electrode and a second external electrode disposed on the one surface of the insulating substrate and connected to two outermost resistor bodies of the plurality of resistor bodies, respectively, in a length direction perpendicular to the width direction, wherein the first external electrode and the second external electrode extend in opposite directions, parallel to the length direction, from respective ends of the two outermost resistor bodies, and further extend in opposite directions, parallel to the width direction, along opposing edges of the insulating substrate, such that the first external electrode and the second external electrode overlap the plurality of internal electrodes in the length direction.
BRIEF DESCRIPTION OF DRAWINGS
The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a schematic perspective view illustrating a chip resistor according to the present disclosure;
FIG. 2 is a plan view illustrating the chip resistor of FIG. 1 when viewed from one surface of an insulating substrate;
FIG. 3 is a cross-sectional view taken along line I-I′ of the chip resistor of FIG. 1;
FIG. 4 is a cross-sectional view taken along line II-II′ of the chip resistor of FIG. 1; and
FIGS. 5A through 5E are views for describing a manufacturing process of the chip resistor according to the present disclosure.
DETAILED DESCRIPTION
Hereinafter, exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.
In addition, herein, the meaning that a component is formed on another component is that a component is formed on another component with the other component interposed therebetween as well as a component is in direct contact with and formed on another component.
Further, herein, end portions may refer to end parts opposing each other, and may refer to a first end or a second end opposing the first end, or refer to one end and the other end. In this case, a region expressed as one end in any description may be expressed as the other end in another description. Similarly, a region expressed as the other end in any description may be expressed as one end in another description.
A “connection” of a component to another component herein conceptually includes an indirect connection through a third component as well as a direct connection between two components. In addition, “electrically connected” conceptually includes a physical connection and a physical disconnection.
Terms “first”, “second”, and the like, herein are used to distinguish one component from another component, and do not limit a sequence, importance, and the like, of the corresponding components. In some cases, a first element may be referred to as a second element. Similarly, a second element may also be referred to as a first element.
The term “an exemplary embodiment” used herein does not refer to the same exemplary embodiment, and is used to emphasize a particular feature or characteristic different from that of another exemplary embodiment. However, exemplary embodiments provided herein are considered to be able to be implemented by being combined in whole or in part one with one another. For example, one element described in a particular exemplary embodiment, even if it is not described in another exemplary embodiment, may be understood as a description related to another exemplary embodiment, unless an opposite or contradictory description is provided therein.
Terms used herein are used only in order to describe an exemplary embodiment rather than limiting the present disclosure. In this case, singular forms include plural forms unless interpreted otherwise in context.
Hereinafter, exemplary embodiments in the present disclosure will be described with reference to the accompanying drawings. In the drawings, shapes, sizes, and the like, of respective components may be exaggerated or shortened for clarity.
Chip Resistor
FIG. 1 is a schematic perspective view illustrating a chip resistor according to the present disclosure.
FIG. 2 is a plan view illustrating the chip resistor of FIG. 1 when viewed from one surface of an insulating substrate.
FIG. 3 is a cross-sectional view taken along line I-I′ of the chip resistor of FIG. 1.
FIG. 4 is a cross-sectional view taken along line II-II′ of the chip resistor of FIG. 1.
Referring to FIGS. 1 through 4, the chip resistor according to the present disclosure may include an insulating substrate 110, a resistor portion 120 disposed on one surface of the insulating substrate 110 and including a plurality of resistor bodies 121 spaced apart from each other and a plurality of internal electrodes 122 connecting the plurality of resistor bodies 121 to each other, and a first external electrode 130A and a second external electrode 130B disposed on one surface of the insulating substrate 110 to be spaced apart from each other and respectively connected to the resistor bodies 121. In addition, the chip resistor may further include at least one of a protective layer 140, a first cover electrode 150A, and a second cover electrode 150B.
The insulating substrate 110 may serve to support the resistor portion 120 and secure strength of the chip resistor.
The insulating substrate 110 may have both end surfaces opposing each other in a length direction L, both side surfaces opposing each other in a width direction W perpendicular to the length direction L, and one surface and the other surface opposing each other in a thickness direction T perpendicular to each of the length direction L and the width direction W. The insulating substrate 110 may have a rectangular parallelepiped shape or a plate shape as a whole, but is not limited thereto.
A material for forming the insulating substrate 110 is not particularly limited, and may be a material having an excellent insulation property, heat dissipation property, and adhesion property to the resistor body 121. For example, the insulating substrate 110 may be formed of a ceramic material such as alumina (Al2O3).
The resistor portion 120 may be disposed on one surface of the insulating substrate 110, and may include the resistor bodies 121 and the internal electrodes 122. The resistor portion 120 may electrically connect the first external electrode 130A and the second external electrode 130B to each other.
The chip resistor according to the present disclosure may include the plurality of resistor bodies 121. The number of resistor bodies 121 is not particularly limited, and may be more than that illustrated in the drawings or be less than that illustrated in the drawings.
In this case, as illustrated in the drawings, the plurality of resistor bodies 121 may be spaced apart from each other in the width direction W perpendicular to the length direction L from the first external electrode 130A toward the second external electrode 130B. It has been illustrated in the drawings that the plurality of resistor bodies 121 are disposed in parallel with each other, but the plurality of resistor bodies 121 are not limited thereto. In addition, according to a design, the plurality of resistor bodies 121 may be spaced apart from each other in the length direction L from the first external electrode 130A toward the second external electrode 130B.
Each of the plurality of resistor bodies 121 may have a first end adjacent to the first external electrode 130A and a second end opposing one first and adjacent to the second external electrode 130B. the first end and the second end of each of the plurality of resistor bodies 121 may oppose each other in the length direction L. Each of the plurality of resistor bodies 121 may be disposed in a region between the first external electrode 130A and the second external electrode 130B. However, the plurality of resistor bodies 121 may have regions overlapping each other for connection with the first external electrode 130A and the second external electrode 130B.
Each of the first end and the second end of each of the plurality of resistor bodies 121 may be connected to one of the internal electrode 122, the first external electrode 130A, and the second external electrode 130B. In this case, each of the first end and the second end of each of the plurality of resistor bodies 121 may be covered with one of the internal electrode 122, the first external electrode 130A, and the second external electrode 130B to be connected to one of the internal electrode 122, the first external electrode 130A, and the second external electrode 130B.
Resistor bodies 121 disposed on the outermost sides in the width direction W among the plurality of resistor bodies 121 may be connected to the first external electrode 130A or the second external electrode 130B. Specifically, one of two resistor bodies 121 disposed on the outermost sides in the width direction W and facing each other in the width direction W may be connected to the first external electrode 130A, and the other of the two resistor bodies 121 may be connected to the second external electrode 130B. For example, the first end of one of two resistor bodies 121 disposed on the outermost sides in the width direction Wand facing each other in the width direction W may be connected to the first external electrode 130A, and the second end of the other of the two resistor bodies 121 may be connected to the second external electrode 130B. Therefore, the resistor portion 120 may be connected to the first external electrode 130A and the second external electrode 130B through the resistor bodies 121 disposed on the outermost sides.
In addition, the first end and the second end of each of resistor bodies 121 other than the resistor bodies 121 disposed on the outermost sides among the plurality of resistor bodies 121 may be connected to the internal electrodes 122. Specifically, the first end and the second end of each of resistor bodies 121 other than the resistor bodies 121 disposed on the outermost sides among the plurality of resistor bodies 121 may be connected, respectively, to the internal electrodes 122 distinguished from each other among the plurality of internal electrodes 122. Therefore, the plurality of resistor bodies 121 may be connected to each other through the plurality of internal electrodes 122 to constitute the resistor portion 120 functioning as one resistor element together with the plurality of internal electrodes 122. However, each of the first end and the second end of one resistor body 121 may be connected to a different resistor body 121 and may not be connected to the same resistor body 121.
A material including at least one of lead (Pd), silver (Ag), ruthenium (Ru), copper (Cu), nickel (Ni), and silicon (Si) may be used as a material for forming the resistor body 121. For example, the resistor body 121 may be formed by printing a paste for forming the resistor body in which at least one of silica (SiO2), ruthenium oxide (RuO2), a copper-nickel (CuNi) alloy, and Pb2Ru2O6.5 is dispersed in a resin on the insulating substrate 110 and then sintering the printed paste for the resistor body.
In addition, the material for forming the resistor body 121 may further include a glass component, and the resistor body 121 may be formed by, for example, printing the paste for forming the resistor body further including glass and then sintering the printed paste for forming the resistor body.
However, the method of forming the resistor body 121 is not limited thereto, and the resistor body 121 may be formed through a sputtering process or the like.
Meanwhile, at least one of the plurality of resistor bodies 121 may have a groove g. The groove g may serve to adjust a resistance value of the resistor portion 120.
The groove g may be formed through a trimming process, and the resistance value of the resistor portion 120 may be finely adjusted through the groove. Specifically, the trimming process may be performed in a manner of measuring the resistance value of the resistor portion 120 while forming the groove g in the resistor body 121 by laser machining or the like, and stopping the formation of the groove g when the resistance value reaches a target resistance value.
Each of the plurality of resistor bodies 121 may have the groove g, and only some of the plurality of resistor bodies 121 may have the groove g. The number, shapes, positions, and the like, of grooves g formed in each of the plurality of resistor bodies 121 may be the same as or be different from each other. It has been illustrated in the drawings that the groove g is formed in a single number only in the resistor bodies 121 disposed on the outermost sides among the plurality of resistor bodies 121, but the number, shapes, positions, and the like, of grooves g are not limited to those illustrated in the drawings.
The groove g may be formed from an edge of the resistor body 121 inwardly of the resistor body 121. For example, the groove g may be formed from an edge of at least one of surfaces of the resistor body 121 opposing each other in the width direction W inwardly of the resistor body 121 in the width direction W. The groove g may penetrate through the resistor body 121 in the thickness direction T, and may not penetrate through the resistor body 121 in the length direction L and the width direction W.
Each of the plurality of internal electrodes 122 may cover parts of the plurality of resistor bodies 121. In this case, each of the plurality of internal electrodes 122 may cover end portions of the plurality of resistor bodies 121.
Each of the plurality of internal electrodes 122 may be spaced apart from each of the first external electrode 130A and the second external electrode 130B. Therefore, each of the plurality of internal electrodes 122 may be indirectly connected to the first external electrode 130A and the second external electrode 130B through the resistor body 121.
The internal electrode 122 may integrally cover end portions of each of resistor bodies 121 neighboring to each other among the plurality of resistor bodies 121 to connect between the neighboring resistor bodies 121 to each other. For example, the internal electrode 122 may integrally cover the first ends of each of the resistor bodies 121 neighboring to each other in the width direction W among the plurality of resistor bodies 121. In this case, the internal electrode 122 may cover the first end of any one of the plurality of resistor bodies 121, and may extend in the width direction W to further cover the first end of a resistor body 121 adjacent to the resistor body 121 covered by the internal electrode 122. In addition, the internal electrode 122 may cover an end portion of the resistor body 121 and may further cover a part of the insulating substrate 110.
Unlike illustrated in the drawings, when the plurality of resistor bodies 121 are spaced apart from each other in the length direction (L), the internal electrode 122 may integrally cover end portions of each of resistor bodies 121 neighboring to each other in the length direction L among the plurality of resistor bodies 121. In this case, the internal electrode 122 may cover the first end of any one of the plurality of resistor bodies 121, and may extend in the length direction L to further cover the first end of a resistor body 121 adjacent to the resistor body 121 covered by the internal electrode 122.
The internal electrode 122 may be disposed in a region between the first external electrode 130A and the resistor body 121 or a region between the second external electrode 130B and the resistor body 121. However, the internal electrode 122 may have a region overlapping at least one of the resistor body 121, the first external electrode 130A, and the second external electrode 130B.
It may be advantageous to use a material having excellent heat dissipation properties and resistance to thermal shock as a material for forming the internal electrode 122. For example, the internal electrode 122 may be formed by printing a conductive paste including at least one of silver (Ag), a silver-palladium (Ag—Pd) alloy, and copper (Cu) on the insulating substrate 110 and the resistor body 121 and then sintering the printed conductive paste.
The internal electrode 122 may include the same material as that of at least one of the first external electrode 130A and the second external electrode 130B. The internal electrode 122 may be formed together with the first external electrode 130A and the second external electrode 130B in the same process as that of the first external electrode 130A and the second external electrode 130B. In this case, it may be advantageous for convenience of a process to form the internal electrode 122 using the same material as that of each of the first external electrode 130A and the second external electrode 130B. However, the internal electrode 122 may include a material different from that of at least one of the first external electrode 130A and the second external electrode 130B.
The resistor portion 120 may have a structure in which the resistor bodies 121 and the internal electrodes 122 are alternately disposed. In this case, the resistor bodies 121 and the internal electrodes 122 may be alternately disposed in a direction perpendicular to each other while respective end portions thereof overlap each other. Therefore, the resistor body 121 and the internal electrodes 122 may be alternately connected to each other, such that the resistor portion 120 may have a zigzag shape, an S shape and the like as a whole. However, the resistor bodies 121 and the internal electrodes 122 do not necessarily need to be disposed in the direction perpendicular to each other.
A current transferred to the resistor portion 120 through the first external electrode 130A may pass alternately through the resistor bodies 121 and the internal electrodes 122 and be then transferred to the second external electrode 130B. Alternatively, a current transferred to the resistor portion 120 through the second external electrode 130B may pass alternately through the resistor bodies 121 and the internal electrodes 122 and be then transferred to the first external electrode 130A. For example, when the current is transmitted to the resistor portion 120 through the first external electrode 130A, the transferred current may pass through the resistor body 121, the internal electrode 122, the resistor body 121, the internal electrode 122, and the resistor body 121, and be then transferred to the second external electrode 130B.
Alternatively, when the current is transmitted to the resistor portion 120 through the second external electrode 130B, the transferred current may pass through the resistor body 121, the internal electrode 122, the resistor body 121, the internal electrode 122, and the resistor body 121, and be then transferred to the first external electrode 130A.
The first external electrode 130A and the second external electrode 130B may be disposed on one surface of the insulating substrate 110 to be spaced apart from each other, and may be each connected to the resistor bodies 121. In this case, each of the first external electrode 130A and the second external electrodes 130B may electrically connect the resistor bodies 121 to each of first and second cover electrodes 150A and 150B to be described later.
The first external electrode 130A and the second external electrode 130B may be disposed on one surface of the insulating substrate 110 so as to face each other in the length direction L. In addition, the first external electrode 130A and the second external electrode 130B may be disposed on the outermost sides in the length direction L on one surface of the insulating substrate 110.
Each of the first external electrode 130A and the second external electrode 130B may extend to each of corners formed by one surface of the insulating substrate 110 and both end surfaces of the insulating substrate 110 opposing each other in the length direction L, but is not limited thereto. Each of the first external electrode 130A and the second external electrode 130B may extend to each of corners formed by one surface of the insulating substrate 110 and both side surfaces of the insulating substrate 110 opposing each other in the width direction W, but is not limited thereto.
Each of the first external electrode 130A and the second external electrode 130B may be formed by printing a conductive paste including at least one of silver (Ag), a silver-palladium (Ag—Pd) alloy, and copper (Cu) on the insulating substrate 110 and the resistor body 121 and then sintering the printed conductive paste.
At least one of the first external electrode 130A and the second external electrode 130B may include the same material as that of the internal electrode 122. The first external electrode 130A and the second external electrode 130B may be formed together with the internal electrode 122 in the same process as that of the internal electrode 122. In this case, it may be advantageous for convenience of a process to form each of the first external electrode 130A and the second external electrode 130B using the same material as that of the internal electrode 122. However, at least one of the first external electrode 130A and the second external electrode 130B may include a material different from that of the internal electrode 122.
The protective layer 140 may be disposed on the resistor portion 120 to serve to protect the resistor portion 120. In addition, the protective layer 140 may serve to significantly reduce damage to the resistor body 121 in the trimming process.
The protective layer 140 may be disposed in a region between the first external electrode 130A and the second external electrode 130B, and may cover parts of each of the first external electrode 130A and the second external electrode 130B according to a design.
At least one of silica (SiO2), epoxy, a phenol resin, and glass may be used as a material for forming the protective layer 140.
Meanwhile, the groove g may extend to the protective layer 140 so as to penetrate the protective layer 140. The reason is that the groove g is formed so as to penetrate both of the resistor body 121 and the protective layer 140 together after the protective layer 140 is disposed on the resistor portion 120, as described later.
The groove g may be formed from an edge of the protective layer 140 inwardly of the protective layer 140. For example, the groove g may be formed from an edge of at least one of surfaces of the protective layer 140 opposing each other in the width direction W inwardly of the protective layer 140 in the width direction W. The groove g may penetrate through the protective layer 140 in the thickness direction T, and may not penetrate through the protective layer 140 in the length direction L and the width direction W.
However, the protective layer 140 may be formed in a region wider than that of the resistor body 121, and thus, the groove g of the protective layer 140 may have a shape in which the groove g of the resistor body 121 extends. For example, the groove g of the protective layer 140 may have a shape in which the groove g of the resistor body 121 extends in the width direction W.
It has been illustrated in the drawings that a thickness of the protective layer 140 on one surface of the insulating substrate 110 is greater than that of each of the first cover electrode 150A and the second cover electrode 150B, but the thickness of the protective layer 140 is not limited thereto. According to a design, in order to easily connect the first cover electrode 150A and the second cover electrode 150B to a mounting substrate, the thickness of the protective layer 140 on one surface of the insulating substrate 110 may be smaller than that of each of the first cover electrode 150A and the second cover electrode 150B.
Each of the first cover electrode 150A and the second cover electrode 150B is connected to each of the first external electrode 130A and the second external electrode 130B.
The first cover electrode 150A and the second cover electrode 150B may be disposed on end portions of the insulating substrate 110, respectively, to be spaced apart from each other. For example, each of the first cover electrode 150A and the second cover electrode 150B may be disposed on each of both end surfaces of the insulating substrate 110 and extend onto one surface and the other surface of the insulating substrate 110 to have a ‘U’ shape.
A material for forming each of the first cover electrode 150A and the second cover electrode 150B may include at least one of nickel (Ni), tin (Sn), copper (Cu), and chromium (Cr). Each of the first cover electrode 150A and the second cover electrode 150B may include one or more metal layers. For example, each of the first cover electrode 150A and the second cover electrode 150B may have a triple metal layer structure in which a nickel (Ni) plating layer and a tin (Sn) plating layer are sequentially disposed on a copper (Cu) plating layer.
Meanwhile, in a high-power product for realizing higher power in a chip having the same size, there is a case where a serpentine cut is formed in a resistor body through a laser trimming process in order to improve power characteristics. In this case, there is a problem that heat is generated due to concentration of a current on the resistor body disposed in a trimming end region.
In the chip resistor according to the present disclosure, the resistor portion 120 in which the plurality of resistor bodies 121 are connected to each other by the internal electrodes 122 having excellent heat dissipation properties and resistance to thermal shock may be provided instead of a single resistor body in which the serpentine cut is formed through the trimming process. The chip resistor capable of efficiently dissipating heat generated due to current concentration through the internal electrodes and resistance to the thermal shock may be provided. As a result, the chip resistor having improved power characteristics in the same size may be provided.
FIGS. 5A through 5E are views for describing a manufacturing process of the chip resistor according to the present disclosure.
Referring to FIG. 5A, the resistor body 121 may be formed on the insulating substrate 110. The resistor body 121 may be formed by printing a paste for forming the resistor body in which at least one of silica (SiO2), ruthenium oxide (RuO2), a copper-nickel (CuNi) alloy, and Pb2Ru2O6.5 is dispersed in a resin on the insulating substrate 110 and then sintering the printed paste for the resistor body. Alternatively, the resistor body 121 may be formed by printing the paste for forming the resistor body further including glass and the sintering the printed paste for forming the resistor body. In this case, the resistor body 121 may exist as a single resistor body 121 that is not spaced apart from each other on the insulating substrate 110.
Next, referring to FIG. 5B, the resistor body 121 may be separated into a plurality of resistor bodies 121 spaced apart from each other. In this case, the resistor body 121 may be separated into the plurality of resistor bodies by removing parts of the resistor body 121 with a laser beam. The process of separating the resistor body 121 into the plurality of resistor bodies 121 with the laser beam may be performed in a manner of executing, plural times, a process of exposing the insulating substrate 110 by laser-machining the resistor body 121 along the length direction L from the first end of the resistor body 121 to the second end of the resistor body 121.
Alternatively, the process of separating the resistor body 121 into the plurality of resistor bodies 121 with the laser beam may be performed between a process of printing the paste for forming the resistor body and a process of sintering the printed paste for the resistor body, unlike described above, but is not limited thereto.
Next, referring to FIG. 5C, the internal electrodes 122 and the external electrodes 130A and 130B connected to the resistor bodies 121. Each of the internal electrodes 122 and the external electrodes 130A and 130B may be formed by printing a conductive paste including at least one of silver (Ag), a silver-palladium (Ag—Pd) alloy, and copper (Cu) on the insulating substrate 110 and the resistor body 121 and then sintering the printed conductive paste. The internal electrodes 122 and the external electrodes 130A and 130B may be formed in the same process, but may be formed separately from each other. The internal electrode 122 may integrally cover the end portions of the resistor bodies 121 adjacent to each other among the plurality of resistor bodies 121, and the external electrodes 130A and 130B may cover the end portions of the resistor bodies 121 disposed on the outermost sides in the width direction W among the plurality of resistor bodies 121.
Next, referring to FIG. 5D, the protective layer 140 may be formed. The protective layer 140 may cover the resistor portion 120 and may further cover the insulating substrate 110. In addition, the protective layer 140 may further cover parts of the external electrodes 130A and 130B, but it may be preferable that the protective layer 140 does not cover regions of the external electrodes 130A and 130B connected to the cover electrodes 150A and 150B. As such, the protective layer 140 may be in contact with one side surface of an extending portion of each of the first and second cover electrodes 150A and 150B. Here, the extending portion of each of the first and second cover electrodes 150A and 150B may refer to a portion extending along the one surface of the insulating substrate 110.
Next, referring to FIG. 5E, the groove g may be formed. The groove g may be formed through a trimming process using laser machining, and the resistance value of the resistor portion 120 may be finely adjusted through the groove. Specifically, the trimming process may be performed in a manner of measuring the resistance value of the resistor portion 120 while forming the groove g in the resistor body 121 and the protective layer 140 by laser machining or the like, and stopping the formation of the groove g when the resistance value reaches a target resistance value.
The groove g may be formed from the edge of each of the resistor body 121 and the protective layer 140 inwardly of each of the resistor body 121 and the protective layer 140. For example, the groove g may be formed from the edges of at least one of surfaces of each of the resistor body 121 and the protective layer 140 opposing each other in the width direction W inwardly of each of the resistor body 121 and the protective layer 140 in the width direction W. The groove g may penetrate through each of the resistor body 121 and the protective layer 140 in the thickness direction T. The groove g may not penetrate through each of the resistor body 121 and the protective layer 140 in the length direction L and the width direction W.
In this case, the resistor body 121 may be damaged in the trimming process, but the protective layer 140 may disposed on the resistor body 121 to significantly reduce the damage to the resistor body 121.
Although not illustrated in the drawings, the first cover electrode 150A and the second cover electrode 150B may further be formed using a plating process and a vapor deposition method such as sputtering alone or a combination thereof.
As set forth above, according to the exemplary embodiment in the present disclosure, the chip resistor having the excellent heat dissipation property and resistance to thermal shock may be provided.
In addition, the chip resistor having the improved electrical characteristics may be provided.
While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present invention as defined by the appended claims.
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17182681
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samsung electro-mechanics co., ltd.
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USA
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B1
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Utility Patent Grant (no pre-grant publication) issued on or after January 2, 2001.
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Open
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Apr 27th, 2022 09:11AM
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Apr 27th, 2022 09:11AM
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Samsung
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krx:005930
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Samsung
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Apr 26th, 2022 12:00AM
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Jan 8th, 2020 12:00AM
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https://www.uspto.gov?id=US11316272-20220426
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Antenna apparatus
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An antenna apparatus includes a feed line; a ground plane surrounding a portion of the feed line; a feed via electrically connected to the feed line and extending from a first side of the feed line; a first end-fire antenna pattern disposed on a first side of at least a portion of the ground plane and spaced apart from the ground plane, and electrically connected to the feed via; a second end-fire antenna pattern disposed on a second side of the feed line opposite the first side of the feed line and spaced apart from the first end-fire antenna pattern; and a core via electrically connecting the first end-fire antenna patterns to the second end-fire antenna pattern.
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11316272
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1. An antenna apparatus, comprising:
a feed line;
a ground plane surrounding a portion of the feed line;
a feed via electrically connected to the feed line and extending from a first side of the feed line;
a first end-fire antenna pattern, disposed on a first side of at least a portion of the ground plane and spaced apart from the ground plane, electrically connected to the feed via;
a second end-fire antenna pattern disposed on a second side of the feed line opposite the first side of the feed line and spaced apart from the first end-fire antenna pattern;
a core via electrically connecting the first end-fire antenna pattern to the second end-fire antenna pattern; and
a core pattern electrically connected to the core via between the first end-fire antenna pattern and the second end-fire antenna pattern.
2. The antenna apparatus of claim 1,
wherein the core via includes a plurality of core vias, and
wherein the second end-fire antenna pattern electrically connects the plurality of core vias to each other.
3. The antenna apparatus of claim 1, wherein the core pattern has a width greater than a width of the core via.
4. The antenna apparatus of claim 1, further comprising:
a plurality of first ground patterns extending from at least a portion of the ground plane such that the first end-fire antenna pattern and the second end-fire antenna pattern are disposed between the plurality of first ground patterns and the ground plane, and the plurality of first ground patterns comprises first protruding portions protruding towards each other.
5. The antenna apparatus of claim 4, wherein the core via is disposed more adjacent to the plurality of first ground patterns than to the feed via.
6. The antenna apparatus of claim 4, further comprising:
a plurality of second ground patterns disposed on a first side of the plurality of first ground patterns and comprising second protruding portions protruding towards each other; and
a plurality of first shielding vias electrically connecting the first protruding portions to the second protruding portions.
7. The antenna apparatus of claim 1, wherein the first end-fire antenna pattern extends diagonally with respect to the feed line.
8. The antenna apparatus of claim 7, wherein a deviation of a width of the second end-fire antenna pattern is greater than a deviation of a width of the first end-fire antenna pattern.
9. The antenna apparatus of claim 1, wherein a spacing distance between the feed line and the second end-fire antenna pattern is larger than a spacing distance between the feed line and the first end-fire antenna pattern.
10. The antenna apparatus of claim 1, further comprising:
a patch antenna pattern disposed on the second side of the feed line farther away from the feed line than the ground plane,
wherein at least a portion of the second end-fire antenna pattern is disposed at a same distance or farther away from the feed line than the patch antenna pattern.
11. An antenna apparatus, comprising:
a feed line;
a ground plane surrounding at least a portion of the feed line;
a first end-fire antenna pattern disposed on a first side of the ground plane, spaced apart from the ground plane, and electrically connected to the feed line;
a second end-fire antenna pattern disposed on an opposite side of the feed line from the first end-fire antenna pattern and spaced apart from the first end-fire antenna pattern;
a core via electrically connecting the first end-fire antenna pattern to the second end-fire antenna pattern; and
a plurality of first ground patterns extending from at least a portion of the ground plane such that the first end-fire antenna pattern and the second end-fire antenna pattern are disposed between the plurality of first ground patterns and the ground plane, and the plurality of first ground patterns comprises first protruding portions protruding towards each other.
12. The antenna apparatus of claim 11, further comprising:
a plurality of second ground patterns disposed on a first side of the plurality of first ground patterns and comprising second protruding portions protruding towards each other; and
a plurality of first shielding vias electrically connecting the first protruding portions to the second protruding portions.
13. The antenna apparatus of claim 12, further comprising:
a plurality of second shielding vias, at least a portion of which is disposed in between the first and second end-fire antenna patterns and the ground plane, and extending from the ground plane away from the feed line.
14. The antenna apparatus of claim 12,
wherein the first end-fire antenna pattern is disposed at a same distance or farther away from the feed line than at least a portion of the plurality of first ground patterns, and
wherein the second end-fire antenna pattern is disposed at a same distance or farther away from the feed line than at least a portion of the plurality of second ground patterns.
15. The antenna apparatus of claim 11,
wherein the first protruding portions protrude towards each other in a region disposed further away from the first side of the ground plane than the first end-fire antenna pattern and the second end-fire antenna pattern, and
wherein a spacing distance between the first protruding portions is larger than a length of the second end-fire antenna pattern.
16. The antenna apparatus of claim 11, wherein each of the plurality of first ground patterns is L-shaped or T-shaped.
17. An antenna apparatus, comprising:
a ground plane extending in a first direction;
a feed line extending from the ground plane in a second direction substantially perpendicular to the first direction;
a first end-fire antenna pattern electrically connected to the feed line and disposed on a first side of the feed line spaced apart from the feed line in a third direction substantially perpendicular to the first direction and the second direction;
a second end-fire antenna pattern disposed on a second side of the feed line opposite the first side of the feed line and spaced apart from the feed line in the third direction;
a core via spaced apart from the feed line in the first direction and the second direction and electrically connecting the first end-fire antenna pattern to the second end-fire antenna pattern; and
a ground pattern comprising a first portion that extends from the ground plane in the second direction and a second portion that extends from the first portion in the first direction.
18. The antenna apparatus of claim 17, wherein the second portion of the ground pattern is spaced apart from the ground plane in the second direction more than both the first end-fire antenna pattern and the second end-fire antenna pattern.
19. The antenna apparatus of claim 17, wherein a point at which the first end-fire antenna pattern is electrically connected to the feed line is spaced apart from the ground plane in the second direction more than the core via.
20. The antenna apparatus of claim 17, wherein the core via is spaced apart from the ground plane in the second direction more than a point at which the first end-fire antenna pattern is electrically connected to the feed line.
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20
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CROSS-REFERENCE TO RELATED APPLICATION(S)
This application claims the benefit under 35 USC 119(a) of Korean Patent Application No. 10-2019-0076304 filed on Jun. 26, 2019 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.
BACKGROUND
1. Field
The following description relates to an antenna apparatus.
2. Description of Background
Mobile communications data traffic has increased on an annual basis. Various techniques have been developed to support the rapid increase in data in wireless networks in real time. For example, conversion of Internet of Things (IoT)-based data into contents, augmented reality (AR), virtual reality (VR), live VR/AR linked with SNS, an automatic driving function, applications such as a sync view (transmission of real-time images at a user viewpoint using a compact camera), and the like, may require communications (e.g., 5G communications, mmWave communications, and the like) which support the transmission and reception of large volumes of data.
Accordingly, there has been a large amount of research on mmWave communications including 5th generation (5G), and the research into the commercialization and standardization of an antenna apparatus for implementing such communications has been increasingly conducted.
A radio frequency (RF) signal of a high frequency band (e.g., 24 GHz, 28 GHz, 36 GHz, 39 GHz, 60 GHz, and the like) may easily be absorbed and lost during transmission, which may degrade quality of communications. Thus, an antenna for communications performed in a high frequency band may require a technical approach different from techniques used in a general antenna, and a special technique such as a separate power amplifier, and the like, may be required to secure antenna gain, integration of an antenna and a radio frequency integrated circuit (RFIC), effective isotropic radiated power (EIRP), and the like.
SUMMARY
This Summary is provided to introduce a selection of concepts in simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
An antenna apparatus which may provide a transmission and reception configuration for a plurality of different frequency bands, may improve an antenna performance, and/or may be easily miniaturized.
In one general aspect, an antenna apparatus includes: a feed line; a ground plane surrounding a portion of the feed line; a feed via electrically connected to the feed line and extending from a first side of the feed line; a first end-fire antenna pattern disposed on a first side of at least a portion of the ground plane and spaced apart from the ground plane, and electrically connected to the feed via; a second end-fire antenna pattern disposed on a second side of the feed line opposite the first side of the feed line and spaced apart from the first end-fire antenna pattern; and a core via electrically connecting the first end-fire antenna patterns to the second end-fire antenna pattern.
The core via may include a plurality of core vias, and the second end-fire antenna pattern may electrically connect the plurality of core vias to each other.
The antenna apparatus may include a core pattern electrically connected to the core via between the first end-fire antenna pattern and the second end-fire antenna pattern and having a width greater than a width of the core via.
The antenna apparatus may include a plurality of first ground patterns extending from at least a portion of the ground plane such that the first end-fire antenna pattern and the second end-fire antenna pattern are disposed between the plurality of first ground patterns and the ground plane, and the plurality of first ground patterns may include first protruding portions protruding towards each other.
The core via may be disposed more adjacent to the plurality of first ground patterns than to the feed via.
The antenna apparatus may include: a plurality of second ground patterns disposed on a first side of the plurality of first ground patterns and including second protruding portions protruding towards each other; and a plurality of first shielding vias electrically connecting the first protruding portions to the second protruding portions.
The first end-fire antenna pattern may extend diagonally with respect to the feed line.
A deviation of a width of the second end-fire antenna pattern may be greater than a deviation of a width of the first end-fire antenna pattern.
A spacing distance between the feed line and the second end-fire antenna pattern may be larger than a spacing distance between the feed line and the first end-fire antenna pattern.
The antenna apparatus may include a patch antenna pattern disposed on the second side of the feed line farther away from the feed line than the ground plane, and at least a portion of the second end-fire antenna pattern may be disposed at a same distance or farther away from the feed line than the patch antenna pattern.
In another general aspect, an antenna apparatus includes a feed line; a ground plane surrounding at least a portion of the feed line; a first end-fire antenna pattern disposed on a first side of the ground plane, spaced apart from the ground plane, and electrically connected to the feed line; a second end-fire antenna pattern disposed on an opposite side of the feed line from the first end-fire antenna pattern and spaced apart from the first end-fire antenna pattern; and a core via electrically connecting the first end-fire antenna pattern to the second end-fire antenna pattern; and a plurality of first ground patterns extending from at least a portion of the ground plane such that the first end-fire antenna pattern and the second end-fire antenna pattern are disposed between the plurality of first ground patterns and the ground plane, and the plurality of first ground patterns includes first protruding portions protruding towards each other.
The antenna apparatus may include: a plurality of second ground patterns disposed on a first side of the plurality of first ground patterns and including second protruding portions protruding towards each other; and a plurality of first shielding vias electrically connecting the first protruding portions to the second protruding portions.
The antenna apparatus may include a plurality of second shielding vias, at least a portion of which is disposed in between the first and second end-fire antenna patterns and the ground plane, and extending from the ground plane away from the feed line.
The first end-fire antenna pattern may be disposed at a same distance or farther away from the feed line than at least a portion of the plurality of first ground patterns, and the second end-fire antenna pattern may be disposed at a same distance or farther away from the feed line than at least a portion of the plurality of second ground patterns.
The first protruding portions may protrude towards each other in a region disposed further away from the first side of the ground plane than the first end-fire antenna pattern and the second end-fire antenna pattern, and a spacing distance between the first protruding portions may be larger than a length of the second end-fire antenna pattern.
Each of the plurality of first ground patterns may be L-shaped or T-shaped.
In another general aspect, an antenna apparatus includes a ground plane extending in a first direction; a feed line extending from the ground plane in a second direction substantially perpendicular to the first direction; a first end-fire antenna pattern electrically connected to the feed line and disposed on a first side of the feed line spaced apart from the feed line in a third direction substantially perpendicular to the first direction and the second direction; a second end-fire antenna pattern disposed on a second side of the feed line opposite the first side of the feed line and spaced apart from the feed line in the third direction; a core via spaced apart from the feed line in the first direction and the second direction and electrically connecting the first end-fire antenna pattern to the second end-fire antenna pattern; and a ground pattern including a first portion that extends from the ground plane in the second direction and a second portion that extends from the first portion in the first direction.
The second portion of the ground pattern may be spaced apart from the ground plane in the second direction more than both the first end-fire antenna pattern and the second end-fire antenna pattern.
A point at which the first end-fire antenna pattern is electrically connected to the feed line may be spaced apart from the ground plane in the second direction more than the core via.
The core via may be spaced apart from the ground plane in the second direction more than a point at which the first end-fire antenna pattern is electrically connected to the feed line.
Other features and aspects will be apparent from the following detailed description, the drawings, and the claims.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1A is a perspective view illustrating an antenna apparatus according to an example.
FIG. 1B is a side view illustrating an antenna apparatus according to an example.
FIG. 10 is a plan view illustrating an antenna apparatus according to an example.
FIG. 2A is a perspective view illustrating an antenna apparatus according to an example.
FIG. 2B is a side view illustrating an antenna apparatus according to an example.
FIG. 2C is a plan view illustrating an arrangement of an antenna apparatus according to an example.
FIG. 3 is a perspective view illustrating an antenna apparatus according to an example.
FIGS. 4A and 4B are views illustrating dimensions of an antenna apparatus according to an example.
FIGS. 5A and 5B are views illustrating a connection member included in the antenna apparatus illustrated in FIGS. 1A through 4B and a lower structure of the connection member.
FIGS. 6A and 6B are plan views illustrating an example of an electronic device in which an antenna apparatus is disposed.
Throughout the drawings and the detailed description, the same reference numerals refer to the same elements. The drawings may not be to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience.
DETAILED DESCRIPTION
The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent to one of ordinary skill in the art. The sequences of operations described herein are merely examples, and are not limited to those set forth herein, but may be changed as will be apparent to one of ordinary skill in the art, with the exception of operations necessarily occurring in a certain order. Also, descriptions of functions and constructions that would be well known to one of ordinary skill in the art may be omitted for increased clarity and conciseness.
The features described herein may be embodied in different forms, and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to one of ordinary skill in the art.
Herein, it is noted that use of the term “may” with respect to an example or embodiment, e.g., as to what an example or embodiment may include or implement, means that at least one example or embodiment exists in which such a feature is included or implemented while all examples and embodiments are not limited thereto.
Throughout the specification, when an element, such as a layer, region, or substrate, is described as being “on,” “connected to,” or “coupled to” another element, it may be directly “on,” “connected to,” or “coupled to” the other element, or there may be one or more other elements intervening therebetween. In contrast, when an element is described as being “directly on,” “directly connected to,” or “directly coupled to” another element, there can be no other elements intervening therebetween.
As used herein, the term “and/or” includes any one and any combination of any two or more of the associated listed items.
Although terms such as “first,” “second,” and “third” may be used herein to describe various members, components, regions, layers, or sections, these members, components, regions, layers, or sections are not to be limited by these terms. Rather, these terms are only used to distinguish one member, component, region, layer, or section from another member, component, region, layer, or section. Thus, a first member, component, region, layer, or section referred to in examples described herein may also be referred to as a second member, component, region, layer, or section without departing from the teachings of the examples.
Spatially relative terms such as “above,” “upper,” “below,” and “lower” may be used herein for ease of description to describe one element's relationship to another element as shown in the figures. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as being “above” or “upper” relative to another element will then be “below” or “lower” relative to the other element. Thus, the term “above” encompasses both the above and below orientations depending on the spatial orientation of the device. The device may also be oriented in other ways (for example, rotated 90 degrees or at other orientations), and the spatially relative terms used herein are to be interpreted accordingly.
The terminology used herein is for describing various examples only, and is not to be used to limit the disclosure. The articles “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises,” “includes,” and “has” specify the presence of stated features, numbers, operations, members, elements, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, members, elements, and/or combinations thereof.
Due to manufacturing techniques and/or tolerances, variations of the shapes shown in the drawings may occur. Thus, the examples described herein are not limited to the specific shapes shown in the drawings, but include changes in shape that occur during manufacturing.
The features of the examples described herein may be combined in various ways as will be apparent after an understanding of the disclosure of this application. Further, although the examples described herein have a variety of configurations, other configurations are possible as will be apparent after an understanding of the disclosure of this application.
Hereinafter, examples of the present disclosure will be described as follows with reference to the attached drawings.
FIG. 1A is a perspective view illustrating an antenna apparatus according to an example. FIG. 1B is a side view illustrating an antenna apparatus according to an example. FIG. 10 is a plan view illustrating an antenna apparatus according to an example.
Referring to FIGS. 1A, 1B, and 1C, an antenna device may include a first end-fire antenna pattern 121a and a second end-fire antenna pattern 122a, and accordingly, the antenna device may provide a transmission and reception configuration for a plurality of different frequency bands.
The first end-fire antenna pattern 121a may be electrically connected to one end of a feed line 110a through a feed via 111a, and may be provided with first and second radio frequency signals from the feed line 110a and may transmit the RF signals in a front direction (e.g., a Y direction), or may provide first and second RF signals received in a front direction to the feed line 110a.
The feed line 110a may be electrically connected to a first wiring via 231a in a connection member 200a, and the first wiring via 231a may be electrically connected to an IC 310a disposed on a lower side (e.g., in a −z direction). The IC 310a may provide the first and second RF signals to the first end-fire antenna pattern 121a and the second end-fire antenna pattern 122a or may be provided with the first and second RF signals through the first wiring via 231a and the feed line 110a.
The feed line 110a may have a structure in which a transmission path of the first RF signal of a first frequency band (e.g., 39 GHz) and a transmission path of the second RF signal of a second frequency band (e.g., 28 GHz) are shared. Accordingly, the number of the feed line 110a may decrease, a size of an area occupied by the RF signal transmission path may decrease in the connection member 200a, and an overall size of the antenna device in the example may be reduced.
For example, the feed line 110a may include first and second feed lines. The first and second feed lines may be electrically connected to poles on one side and the other side of the first end-fire antenna pattern 121a, respectively.
A portion 212a of the feed line 110a may be surrounded by at least portions of ground planes 201a, 202a, 203a, 204a, 205a, and 206a, which are included in the connection member 200a. Accordingly, the first and second end-fire antenna patterns 121a and 122a may form a radiation pattern around end lines of the ground planes 201a, 202a, 203a, 204a, 205a, and 206a.
The first and second end-fire antenna patterns 121a and 122a may resonate with respect to the first frequency band and/or the second frequency band, respectively, may receive energy corresponding to the first and second RF signals, and may externally irradiate the energy.
An insulating layer 240a may surround the first and second end-fire antenna patterns 121a and 122a, and may have a dielectric constant (Dk) higher than that of air. The dielectric constant may affect resonance frequencies of the first and second end-fire antenna patterns 121a and 122a.
The connection member 200a may reflect first and second RF signals among the first and second RF signals irradiated by the first and second end-fire antenna patterns 121a and 122a towards the connection member 200a, and accordingly, radiation patterns of the first and second end-fire antenna patterns 121a and 122a may be focused in a front direction (e.g., a Y direction). Accordingly, gains of the first and second end-fire antenna patterns 121a and 122a may improve.
At least portions of a plurality of second shielding vias 145a may be disposed in rear of the first and second end-fire antenna patterns 121a and 122a and may extend to an upper side from the ground planes 201a, 202a, 203a, 204a, 205a, and 206a. The plurality of second shielding vias 145a may improve a reflection performance of the connection member 200a with respect to the first and second RF signals.
Resonance of the first and second end-fire antenna patterns 121a and 122a may be generated on the basis of a resonance frequency determined by combination of inductance and capacitance corresponding to the first and second end-fire antenna patterns 121a and 122a and a peripheral structure of the first and second end-fire antenna patterns 121a and 122a.
Each of the first and second end-fire antenna patterns 121a and 122a may have a bandwidth based on an intrinsic resonance frequency determined by intrinsic elements (e.g., a form, a size, a thickness, a spacing distance, a dielectric constant of an insulating layer, and the like) and an extrinsic resonance frequency determined by electromagnetic coupling with an adjacent pattern and/or a via.
The first end-fire antenna pattern 121a may have a size smaller than a size of the second end-fire antenna pattern 122a, and may thus have inductance and/or capacitance less than inductance and/or capacitance determined based on intrinsic elements of the second end-fire antenna pattern 122a. Thus, the first end-fire antenna pattern 121a may dominantly resonate with respect to the first RF signal having a relatively short wavelength among the first and second RF signals. The second end-fire antenna pattern 122a may dominantly resonate with respect to the second RF signal.
The feed via 111a may electrically connect the first end-fire antenna pattern 121a to the feed line 110a. The first end-fire antenna pattern 121a may be disposed on a lower side of the feed line 110a by the feed via 111a.
A vector element taken in −Z direction of the first RF signal of the first end-fire antenna pattern 121a may be added to the first RF signal in accordance with provision of a path taken in the −Z direction by the feed via 111a. Accordingly, a radiation pattern of the first end-fire antenna pattern 121a may be inclined in the −Z direction on a front side (e.g., a Y direction).
A core via 115a may electrically connect the first end-fire antenna pattern 121a and the second end-fire antenna pattern 122a to each other.
The core via 115a may have a relatively long length such that the second end-fire antenna pattern 122a may be disposed on an upper level (+Z direction) with respect to a level of the feed line 110a.
A vector element taken in a +Z direction of the second RF signal of the second end-fire antenna pattern 122a may be added to the second RF signal in accordance with provision of a path taken in a +Z direction by the core via 115a. Accordingly, a radiation pattern of the second end-fire antenna pattern 122a may be inclined in the +Z direction on a front side (e.g., a Y direction).
Accordingly, a radiation pattern of the first end-fire antenna pattern 121a may be slightly inclined in the −Z direction, and a radiation pattern of the second end-fire antenna pattern 122a may be slightly inclined in the +Z direction.
Accordingly, radiation patterns of the first and second end-fire antenna patterns 121a and 122a may be spaced apart from each other, thereby reducing electromagnetic interference between the first and second end-fire antenna patterns 121a and 122a and improving a gain related to the first and second RF signals.
A length of the core via 115a may be longer than a length of the feed via 111a (in the Z direction), and a length of the feed via 111a and a length of the core via 115a may work as factors affecting resonance frequencies of the first and second end-fire antenna patterns 121a and 122a.
A length of the feed via 111a may correspond to the first RF signal having a relatively short length among the first and second RF signals, and a length of the core via 115a may correspond to the second RF signal having a relatively long wavelength among the first and second RF signals.
As the core via 115a is configured to extend from the first end-fire antenna pattern 121a disposed on a level lower (in the Z direction) than a level of the feed line 110a, a length of the core via 115a may easily be elongated.
Accordingly, the first and second end-fire antenna patterns 121a and 122a may easily add resonance points for the first and second RF signals, respectively, thereby easily widening first and second bandwidths corresponding to first and second frequencies.
Also, due to the structure of the core via 115a and the feed via 111a extending in different directions, a difference in heights between the first and second end-fire antenna patterns 121a and 122a may increase.
Thus, points at which radiation patterns of the first and second end-fire antenna patterns 121a and 122a are formed may be spaced apart from each other, and radiation patterns of the first and second end-fire antenna patterns 121a and 122a may thus be spaced apart from each other. Accordingly, electromagnetic interference between the first and second end-fire antenna patterns 121a and 122a may be reduced, and a gain related to the first and second RF signals may improve.
For example, the core via 115a may include a plurality of core vias, and the second end-fire antenna pattern 122a may electrically connect the plurality of core vias. To this end, the second end-fire antenna pattern 122a may be configured as a closed-type, which may be different from the open-type first end-fire antenna pattern 121a. As the open-type antenna pattern and the closed-type antenna pattern may form radiation patterns by different electromagnetic principles, electromagnetic interference between first and second radiation patterns of the first and second end-fire antenna patterns 121a and 122a may be reduced. Accordingly, gains related to the first and second RF signals may improve.
Referring to FIGS. 1A, 1B, and 10, the antenna apparatus may further include core patterns 116a, 117a, 118a, and 119a electrically connected to the core via 115a between the first and second end-fire antenna patterns 121a and 122a and each having a width (in the X and Y directions) greater than a width of the core via 115a.
A width of each of the core patterns 116a, 117a, 118a, and 119a taken in a horizontal direction (e.g., an X direction and/or a Y direction) may work as a factor affecting resonance frequencies of the first and second end-fire antenna patterns 121a and 122a.
For example, when a width of each of the core patterns 116a, 117a, 118a, and 119a taken in a horizontal direction is optimized to one of the first and second resonance frequencies of the first and second end-fire antenna patterns 121a and 122a, a width of each of the core patterns 116a, 117a, 118a, and 119a taken in a horizontal direction may work as a filtering element for the other one of the first and second resonance frequencies.
Accordingly, the core patterns 116a, 117a, 118a, and 119a may increase electromagnetic isolation between the first and second end-fire antenna patterns 121a and 122a.
Also, the core patterns 116a, 117a, 118a, and 119a may be electromagnetically coupled to a plurality of first ground patterns 131a, 132a, 133a, 134a, 135a, and 136a (collectively 130a), and the electromagnetic coupling of the core patterns 116a, 117a, 118a, and 119a may work as a factor affecting resonance frequencies of the first and second end-fire antenna patterns 121a and 122a.
Referring to FIGS. 1A, 1B, and 10, the antenna apparatus may further include the plurality of first ground patterns 131a, 132a, 133a, 134a, 135a, and 136a, a plurality of second ground patterns 181a, 182a, 183a, 184a, 185a and 186a (collectively second ground patterns 180a), a plurality of first shielding vias 145a, and the second shielding vias 245a.
The plurality of first ground patterns 131a, 132a, 133a, 134a, 135a, and 136a may extend from at least portions of the plurality of ground planes 201a, 202a, 203a, 204a, 205a, and 206a, respectively, to be disposed between the first and second end-fire antenna patterns 121a and 122a, and may have protruding portions protruding towards each other on front regions of the plurality of ground planes 201a, 202a, 203a, 204a, 205a, and 206a.
For example, each of the plurality of first ground patterns 131a, 132a, 133a, 134a, 135a, and 136a may have an L-shaped form or a T-shaped form.
Accordingly, a first spacing distance taken in the X direction between the protruding portions of the plurality of first ground patterns 131a, 132a, 133a, 134a, 135a, and 136a may be shorter than a second spacing distance taken in the X direction between rear portions of the first ground patterns 131a, 132a, 133a, 134a, 135a, and 136a.
The first and second spacing distances taken in the X direction may work as factors affecting resonance frequencies of the first and second end-fire antenna patterns 121a and 122a.
Thus, the plurality of first ground patterns 131a, 132a, 133a, 134a, 135a, and 136a may provide impedance corresponding to the first spacing distance taken in the X direction to the first end-fire antenna pattern 121a, and may provide impedance corresponding to the second spacing distance taken in the X direction to the second end-fire antenna pattern 122a. Accordingly, the first and second end-fire antenna patterns 121a and 122a may easily improve gains or may easily broaden bandwidths.
The core via 115a may be disposed more adjacent to the plurality of first ground patterns 131a, 132a, 133a, 134a, 135a, and 136a than the feed via 111a.
Accordingly, the core via 115a may be electromagnetically coupled to the protruding portions of the plurality of first ground patterns 131a, 132a, 133a, 134a, 135a, and 136a in an efficient manner.
The plurality of second ground patterns 181a, 182a, 183a, 184a, 185a, and 186a may be disposed on upper portions of the plurality of first ground patterns 131a, 132a, 133a, 134a, 135a, and 136a and may be spaced apart from each other, and may having protruding portions protruding towards each other.
The plurality of first shielding vias 145a may electrically connect the protruding portions of the first and second ground patterns 131a, 132a, 133a, 134a, 135a, 136a, 181a, 182a, 183a, 184a, 185a, and 186a. The plurality of first shielding vias 145a may be electromagnetically coupled to the core via 115a.
The protruding structures of the plurality of second ground patterns 181a, 182a, 183a, 184a, 185a, and 186a may work as factors affecting resonance frequencies of the first and second end-fire antenna patterns 121a and 122a. Thus, the first and second end-fire antenna patterns 121a and 122a may easily improve gains or may easily widen bandwidths.
The first end-fire antenna pattern 121a may be disposed on a level lower than or at the same level as a level of at least portions of the plurality of first ground patterns 131a, 132a, 133a, 134a, 135a, and 136a. The second end-fire antenna pattern 122a may be disposed on a level higher than or at the same level as at least portions of the plurality of second ground patterns 181a, 182a, 183a, 184a, 185a, and 186a.
Accordingly, a spacing distance between the first and second end-fire antenna patterns 121a and 122a taken in the Z direction may easily be elongated, and electromagnetic interference between the first and second RF signals may be reduced. Also, by including the plurality of first and second ground patterns 131a, 132a, 133a, 134a, 135a, 136a, 181a, 182a, 183a, 184a, 185a, and 186a, an overall size of the antenna apparatus may not substantially increase even when a spacing distance between the first and second end-fire antenna patterns 121a and 122a in the Z direction increases.
The first and second ground patterns 131a, 132a, 133a, 134a, 135a, 136a, 181a, 182a, 183a, 184a, 185a, and 186a may protrude more forward than the first and second end-fire antenna patterns 121a and 122a, and may protrude by lengths at which the protruding portions do not block at least portions of the front regions of the first and second end-fire antenna patterns 121a and 122a.
Accordingly, a shortest spacing distance between a portion and the other portion of each of the first and second ground patterns 131a, 132a, 133a, 134a, 135a, 136a, 181a, 182a, 183a, 184a, 185a, and 186a may be greater than a length of the second end-fire antenna pattern 122a.
Accordingly, the protruding portions of the first and second ground patterns 131a, 132a, 133a, 134a, 135a, 136a, 181a, 182a, 183a, 184a, 185a, and 186a may not substantially interfere with formation of radiation patterns of the first and second end-fire antenna patterns 121a and 122a, and thus, the first and second end-fire antenna patterns 121a and 122a may secure relatively high gains.
Referring to FIG. 1B, the antenna apparatus may further include a patch antenna pattern 1110a disposed on a level higher than levels of the plurality of ground planes 201a, 202a, 203a, 204a, 205a, and 206a.
The patch antenna pattern 1110a may be electrically connected to a second feed via 1120a and may remotely transmit and receive a third RF signal in the Z direction, and may be electromagnetically coupled to an upper coupling pattern 1115a, thereby widening a bandwidth. The patch antenna pattern 1110a may be surrounded by a plurality of patch antenna ground patterns 1101a, 1102a, 1103a, 1104a, 1105a, and 1106a (collectively patch antenna ground patterns 1100a).
The plurality of patch antenna ground patterns 1101a, 1102a, 1103a, 1104a, 1105a, and 1106a may be electrically connected to the plurality of second ground patterns 181a, 182a, 183a, 184a, 185a, and 186a.
The second feed via 1120a may be electrically connected to a second wiring via 232a. The first and second wiring vias 231a and 232a may be electrically connected to an IC 310a through an electrical interconnect structure 242a. The IC 310a may receive or transmit a base signal (e.g., an IF signal or a baseband signal) through a mount electrical interconnect structure 213a.
At least a portion of the second end-fire antenna pattern 122a may be disposed on a level higher than or at the same level as a level of the patch antenna pattern 1110a. Accordingly, a spacing distance between the first and second end-fire antenna patterns 121a and 122a taken in the Z direction may easily be elongated, thereby reducing electromagnetic interference between the first and second RF signals.
Referring to FIGS. 1A through 10, the connection member 200a may have a structure in which the plurality of ground planes 201a, 202a, 203a, 204a, 205a, and 206a are stacked. The number of the plurality of ground planes 201a, 202a, 203a, 204a, 205a, and 206a is not limited to any particular number.
At least one of the plurality of ground planes 201a, 202a, 203a, 204a, 205a, and 206a may surround a portion 212a of the feed line 110a, and may be disposed on rear regions of the first and second end-fire antenna patterns 121a and 122a. Accordingly, the plurality of ground planes 201a, 202a, 203a, 204a, 205a, and 206a may reflect the first and second RF signals radiated from the first and second end-fire antenna patterns 121a and 122a. Thus, the plurality of ground planes 201a, 202a, 203a, 204a, 205a, and 206a may work as reflectors in relation to the first and second end-fire antenna patterns 121a and 122a, thereby improving gains of the first and second end-fire antenna patterns 121a and 122a.
FIG. 2A is a perspective view illustrating an antenna apparatus according to an example. FIG. 2B is a side view illustrating an antenna apparatus according to an example.
Referring to FIGS. 2A and 2B, a core via 115a may be disposed further forward (in the +Y direction) than a feed via 111a.
FIG. 2C is a plan view illustrating an arrangement of an antenna apparatus according to an example.
Referring to FIG. 2C, a plurality of second end-fire antenna patterns 122a and 122d may be arranged in the X direction, and may focus radiation patterns in the Y direction.
The configuration of one of the plurality of second end-fire antenna patterns 122a and 122d may be different from the configuration of the other.
FIG. 3 is a perspective view illustrating an antenna apparatus according to an example.
Referring to FIG. 3, a first end-fire antenna pattern 121b and a second end-fire antenna pattern 122c may be configured to be in parallel to a plurality of ground planes 201a, 202a, 203a, 204a, 205a, and 206a.
FIGS. 4A and 4B are views illustrating dimensions of an antenna apparatus according to an example.
Referring to FIG. 4A, a first end-fire antenna pattern 121a may be configured to extend in a diagonal direction by an offset with respect to a feed line 110a.
Accordingly, a second length L2 of the first end-fire antenna pattern 121a may be flexibly adjusted by adjusting a direction of the extending portion of the first end-fire antenna pattern 121a, extending from the feed line 110a. Accordingly, a bandwidth of the first end-fire antenna pattern 121a may be flexibly designed.
A deviation between a third width W3 and a 3-2th width W3_2 of a second end-fire antenna pattern 122a may be greater than a deviation of a second width W2 of the first end-fire antenna pattern 121a.
Accordingly, the first and second end-fire antenna patterns 121a and 122a may easily have different resonance frequencies, thereby improving gains and/or bandwidths of the first and second end-fire antenna patterns 121a and 122a.
Also, a spacing distance (H2-H1) between the feed line 110a and the second end-fire antenna pattern 122a in upwards and downward directions (+/−Z direction) may be longer than a spacing distance H1 between the feed line 110a and the first end-fire antenna pattern 121a in upwards and downward directions (+/−Z direction).
Accordingly, the spacing distance between the first and second end-fire antenna patterns 121a and 122a taken in the Z direction may easily be elongated, thereby reducing electromagnetic interference between the first and second RF signals.
Referring to FIG. 4B, each of first and second ground patterns 130b and 180b may have a first length SWx1 taken in the X direction and a second length SWx2 taken in the X direction, and may have a first length SWy1 taken in the Y direction, a second length SWy2 taken in the Y direction, and a third length SWy3 taken in the Y direction.
The first length SWx1 taken in the X direction and the second length SWx2 taken in the X direction may be configured such that protruding portions of the first and second ground patterns 130b and 180b may be disposed further forward than the first and second end-fire antenna patterns, but the configuration thereof is not limited thereto.
The second length SWx2 taken in the X direction may be configured such that a front side of at least a portion of the first and second end-fire antenna patterns may not be blocked, but embodiment configuration thereof is not limited thereto.
FIGS. 5A and 5B are views illustrating a connection member included in the antenna apparatus illustrated in FIGS. 1A through 4B and a lower structure of the connection member.
Referring to FIG. 5A, an antenna apparatus may include at least portions of a connection member 200, an IC 310, an adhesive member 320, an electrical interconnect structure 330, an encapsulant 340, a passive component 350, and a sub-substrate 410.
The connection member 200 may have a structure similar to a structure of the connection member 200a described with reference to FIGS. 1A through 4B.
The IC 310 may be the same as the IC 310a described in the aforementioned examples, and may be disposed on a lower side of the connection member 200. The IC 310 may be electrically connected to a wiring line of the connection member 200 and may transmit or receive an RF signal. The IC 310 may also be electrically connected to a ground plane of the connection member 200 and may be provided with ground. For example, the IC 310 may generate a converted signal by performing at least portions of frequency conversion, amplification, filtering, a phase control, and power generation.
The adhesive member 320 may allow the IC 310 and the connection member 200 to be adhered to each other.
The electrical interconnect structure 330 may electrically connect the IC 310 to the connection member 200. For example, the electrical interconnect structure 330 may have a structure such as a solder ball, a pin, a land, a pad, and the like. The electrical interconnect structure 330 may have a melting point lower than melting points of a wiring line and a ground plane of the connection member 200 and may electrically connect the IC 310 and the connection member 200 to each other through a required process using the low melting point.
The encapsulant 340 may encapsulate at least a portion of the IC 310, and may improve a heat dissipation performance and a protection performance against impacts. For example, the encapsulant 340 may be implemented by a photoimageable encapsulant (PIE), an Ajinomoto build-up film (ABF), an epoxy molding compound (EMC), and the like.
The passive component 350 may be disposed on a lower surface of the connection member 200, and may be electrically connected to a wiring line and/or a ground plane of the connection member 200 through the interconnect structure 330.
The sub-substrate 410 may be disposed on a lower surface of the connection member 200, and may be electrically connected to the connection member 200 to receive an intermediate frequency (IF) signal or a baseband signal from an external entity and to transmit the signal to the IC 310, or to receive an IF signal or a baseband signal from the IC 310 and to transmit the signal to an external entity. A frequency (e.g., 24 GHz, 28 GHz, 36 GHz, 39 GHz, 60 GHz) of the RF signal may be greater than a frequency (e.g., 2 GHz, 5 GHz, 10 GHz, and the like) of the IF signal.
For example, the sub-substrate 410 may transmit an IF signal or a baseband signal to the IC 310 through a wiring line included in an IC ground plane of the connection member 200, or may receive the signal from the IC 310. As a first ground plane of the connection member 200 is disposed between the IC ground plane and a wiring line, an IF signal or a baseband signal and an RF signal may be electrically isolated from each other in an antenna module.
Referring to FIG. 5B, the antenna apparatus may include at least portions of a shielding member 360, a connector 420, and a chip antenna 430.
The shielding member 360 may be disposed on a lower side of the connection member 200 and may enclose the IC 310, together with the connection member 200. For example, the shielding member 360 may cover or conformally shield the IC 310 and the passive component 350 together, or may separately cover or compartment-shield the IC 310 and the passive component 350. For example, the shielding member 360 may have a hexahedral shape in which one surface is open, and may have an accommodating space having a hexahedral form by being combined with the connection member 200. The shielding member 360 may be implemented by a material having relatively high conductivity such as copper, such that the shielding member 360 may have a skin depth, and the shielding member 360 may be electrically connected to a ground plane of the connection member 200. Accordingly, the shielding member 360 may reduce electromagnetic noise which the IC 310 and the passive component 350 receive.
The connector 420 may have a connection structure of a cable (e.g., a coaxial cable or a flexible PCB), may be electrically connected to the IC ground plane of the connection member 200, and may work similarly to the above-described sub-substrate 410. Accordingly, the connector 420 may be provided with an IF signal, a baseband signal, and/or power from a cable, or may provide an IF signal and/or a baseband signal to a cable.
The chip antenna 430 may transmit or receive an RF signal in addition to the antenna apparatus. For example, the chip antenna 430 may include a dielectric block having a dielectric constant higher than that of an insulating layer, and a plurality of electrodes disposed on both surfaces of the dielectric block. One of the plurality of electrodes may be electrically connected to a wiring line of the connection member 200, and the other one of the plurality of electrodes may be electrically connected to a ground plane of the connection member 200.
FIGS. 6A and 6B are plan views illustrating an example of an electronic device in which an antenna apparatus is disposed.
Referring to FIG. 6A, an antenna module including an antenna apparatus 100g, a patch antenna pattern 1110g, and a dielectric layer 1140g may be disposed adjacent to a side surface boundary of an electronic device 700g on a set substrate 600g of the electronic device 700g.
The electronic device 700g may be implemented as a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game, a smart watch, an Automotive component, or the like, but an example of the electronic device 700g is not limited thereto.
A communication module 610g and a baseband circuit 620g may further be disposed on the set substrate 600g. The antenna module may be electrically connected to the communication module 610g and/or the baseband circuit 620g through a coaxial cable 630g.
The communication module 610g may include at least portions of a memory chip such as a volatile memory (e.g., a DRAM), a non-volatile memory (e.g., a ROM), a flash memory, or the like; an application processor chip such as a central processor (e.g., a CPU), a graphics processor (e.g., a GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like; and a logic chip such as an analog-to-digital converter, an application-specific integrated circuit (ASIC), or the like.
The baseband circuit 620g may generate a base signal by performing analog-to-digital conversion, and amplification, filtering, and frequency conversion on an analog signal. A base signal input to and output from the baseband circuit 620g may be transferred to the antenna module through a cable.
For example, the base signal may be transferred to an IC through an electrical interconnect structure, a cover via, and a wiring line. The IC may cover the base signal into an RF signal of mmWave band.
Referring to FIG. 6B, a plurality of antenna modules each including an antenna apparatus 100i and a patch antenna pattern 1110i may be disposed adjacent to a center of a side of an electronic device 700i having a polygonal shape on a set substrate 600i of the electronic device 700i, and a communication module 610i and a baseband circuit 620i may further be disposed on the set substrate 600i. The antenna apparatus and the antenna module may be electrically connected to the communication module 610i and/or the baseband circuit 620i through a coaxial cable 630i.
The end-fire antenna pattern, the feed line, the feed via, the core via, the wiring via, the ground plane, the ground pattern, the patch antenna pattern, the shielding via, and the electrical interconnect structure described in the example embodiments may include a metal material (e.g., a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof), and may be formed by a plating method such as a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, a sputtering method, a subtractive method, an additive method, a semi-additive process (SAP), a modified semi-additive process (MSAP), or the like, but examples of the material and the method are not limited thereto.
The dielectric layer and/or the insulating layer described in the example embodiments may be implemented by a material such as FR4, a liquid crystal polymer (LCP), low temperature co-fired ceramic (LTCC), a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the above-described resin is impregnated in a core material, such as a glass fiber (or a glass cloth or a glass fabric), together with an inorganic filler, prepreg, a Ajinomoto build-up film (ABF), FR-4, bismaleimide triazine (BT), a Photoimagable Dielectric (PID) resin, a general copper clad laminate (CCL), glass or a ceramic-based insulating material, or the like. The dielectric layer and/or the insulating layer may fill at least a portion of a position of the antenna apparatus in which the end-fire antenna pattern, the feed line, the feed via, the core via, the wiring via, the ground plane, the ground pattern, the patch antenna pattern, the shielding via, and the electrical interconnect structure are not disposed.
The RF signal described in the example embodiments may include protocols such as wireless fidelity (Wi-Fi) (Institute of Electrical And Electronics Engineers (IEEE) 802.11 family, or the like), worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, or the like), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high speed packet access+(HSPA+), high speed downlink packet access+(HSDPA+), high speed uplink packet access+(HSUPA+), enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G, 4G, and 5G protocols, and any other wireless and wired protocols designated after the abovementioned protocols, but an example embodiment thereof is not limited thereto.
According to the aforementioned example embodiments, the antenna apparatus may provide a transmission and reception means for a plurality of different frequency bands, may improve an antenna performance (e.g., a gain, a bandwidth, directivity, a transmission and reception rate, and the like), and/or may be easily miniaturized.
While this disclosure includes specific examples, it will be apparent to one of ordinary skill in the art that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed to have a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or replaced or supplemented by other components or their equivalents. Therefore, the scope of the disclosure is defined not by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.
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16737063
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samsung electro-mechanics co., ltd.
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USA
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B2
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Utility Patent Grant (with pre-grant publication) issued on or after January 2, 2001.
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Open
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Apr 27th, 2022 09:11AM
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Apr 27th, 2022 09:11AM
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Samsung
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krx:005930
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Samsung
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Apr 26th, 2022 12:00AM
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Apr 15th, 2020 12:00AM
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https://www.uspto.gov?id=US11315735-20220426
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Multilayered capacitor and board including the same mounted thereon
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Provided is a multilayer capacitor and a board on which the multilayer capacitor is mounted. The multilayer capacitor includes a capacitor body including first to six surfaces, first and second dielectric layers, and first and second internal electrodes; first and second external electrodes disposed on the first surface of the capacitor body; the first and second dielectric layers are alternately layered in a first direction such that the first internal electrode of the first dielectric layer overlaps the second internal electrode of the second dielectric layer in the first direction, and the second internal electrode of the first dielectric layer overlaps the first internal electrode of the second dielectric layer in the first direction.
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11315735
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1. A multilayer capacitor, comprising:
a capacitor body including first and second surfaces opposing each other in a thickness direction of the capacitor body, third and fourth surfaces connected to the first and second surfaces and opposing each other in a length direction of the capacitor body, fifth and sixth surfaces connected to the first and second surfaces and to the third and fourth surfaces and opposing each other in a width direction of the capacitor body, and including first and second dielectric layers, a plurality of first internal electrodes, and a plurality of second internal electrodes alternately layered in the width direction in which the fifth and sixth surfaces oppose each other;
a first external electrode disposed on the first surface of the capacitor body and connected to the plurality of first internal electrodes; and
a second external electrode disposed on the first surface of the capacitor body, spaced apart from the first external electrode, and connected to the plurality of second internal electrodes,
wherein portions of the first and second internal electrodes are disposed on a first dielectric layer and are spaced apart from each other, and other portions of the first and second internal electrodes are disposed on a second dielectric layer and are spaced apart from each other, and
wherein the first and second dielectric layers are alternately layered in the width direction such that the first internal electrode of the first dielectric layer overlaps the second internal electrode of the second dielectric layer in the width direction, and the second internal electrode of the first dielectric layer overlaps the first internal electrode of the second dielectric layer in the width direction,
wherein the first internal electrode includes:
a 1-1st connection portion disposed on the first dielectric layer, having an end extending from the first surface of the capacitor body, and connected to the first external electrode;
a 1-2nd connection portion disposed on the second dielectric layer, having an end extending from the first surface of the capacitor body, and connected to the first external electrode;
a 1-1st internal electrode disposed on the first dielectric layer, and extending from the 1-1st connection portion in the length direction; and
a 1-2nd internal electrode disposed on the second dielectric layer, configured to not overlap the 1-1st internal electrode in the width direction, and extending from the 1-2nd connection portion in the length direction,
wherein the second internal electrode includes:
a 2-1st connection portion disposed on the first dielectric layer, having an end extending from the first surface of the capacitor body, and connected to the second external electrode;
a 2-2nd connection portion disposed on the second dielectric layer, having an end extending from the first surface of the capacitor body, and connected to the second external electrode;
a 2-1st internal electrode disposed on the first dielectric layer, configured to overlap the 1-2nd internal electrode in the width direction, and extending from the 2-1st connection portion in a direction opposite to the length direction; and
a 2-2nd internal electrode disposed on the second dielectric layer, configured to overlap the 1-1st internal electrode in the width direction, and extending from the 2-2nd connection portion in the direction opposite to the length direction, and
wherein, in the width direction, each conductive pattern extending from the 1-1st connection portion in the length direction overlaps one conductive pattern extending from the 2-2nd connection portion in the direction opposite to the length direction.
2. The multilayer capacitor of claim 1, wherein the 1-1st internal electrode is symmetrical to the 2-2nd internal electrode in the length direction and the 1-2nd internal electrode is symmetrical to the 2-1st internal electrode in the length direction.
3. The multilayer capacitor of claim 1, wherein the first and second internal electrodes are spaced apart from the second, third, and fourth surfaces of the capacitor body in the capacitor body.
4. The multilayer capacitor of claim 1, wherein each of a combined structure of the 1-2nd internal electrode and the 1-2nd connection portion and a combined structure of the 2-1st internal electrode and the 2-1st connection portion has a “¬”-shaped form.
5. The multilayer capacitor of claim 1,
wherein the first internal electrode further includes:
another 1-2nd internal electrode disposed on the second dielectric layer, configured to not overlap the 1-1st internal electrode in the width direction, and extending from the 1-2nd connection portion in the length direction;
wherein the second internal electrode further includes:
another 2-1st internal electrode disposed on the first dielectric layer, configured to overlap the another 1-2nd internal electrode in the width direction, and extending from the 2-1st connection portion in the direction opposite to the length direction.
6. The multilayer capacitor of claim 5, wherein the first and second internal electrodes are spaced apart from the second, third, and fourth surfaces of the capacitor body in the capacitor body.
7. The multilayer capacitor of claim 5,
wherein the first internal electrode further includes:
another 1-1st internal electrode disposed on the first dielectric layer and extending from the 1-1st connection portion in the length direction;
wherein the second internal electrode further includes:
another 2-2nd internal electrode disposed on the second dielectric layer, configured to overlap the another 1-1st internal electrode in the width direction, and extending from the 2-2nd connection portion in the direction opposite to the length direction.
8. The multilayer capacitor of claim 7, wherein the first and second internal electrodes are spaced apart from the second, third, and fourth surfaces of the capacitor body in the capacitor body.
9. A board on which the multilayer capacitor of claim 1 is mounted, the board comprising:
a board having first and second electrode pads on one surface; and
the multilayer capacitor,
wherein the first and second external electrodes are mounted on and connected to the first and second electrode pads, respectively.
10. The multilayer capacitor of claim 1, wherein each of the first and second external electrodes is disposed only on the first surface.
11. The multilayer capacitor of claim 1, wherein the 1-1st connection portion overlaps the 2-2nd connection portion in the width direction, and
the 2-1st connection portion overlaps the 2-2nd connection portion in the width first direction.
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11
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CROSS-REFERENCE TO RELATED APPLICATION(S)
This application claims benefit of priority to Korean Patent Application No. 10-2019-0167022 filed on Dec. 13, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
TECHNICAL FIELD
The present disclosure relates to a multilayer capacitor and a board including the same mounted thereon.
BACKGROUND
As a thickness of a smartphone has been reduced, an electronic component has been designed to have a reduced weight and thickness and improved integration density, and a greater number of passive than active elements have been applied to an electronic device.
There has been increased interest in a multilayer capacitor among such passive elements. That is because a greater number of multilayer capacitors may be mounted on a circuit than other types of passive elements, and with the development of microelectronics technology, a decoupling capacitor having increased capacitance and a reduced connection length has been required. Accordingly, the importance of a multilayer capacitor in an electrical circuit has increased.
Also, such a multilayer capacitor has been required to have low equivalent series resistance (ESR) to implement high efficiency with the same capacitance and to have low equivalent serial inductance (ESL) to significantly reduce a ripple of a power current.
SUMMARY
An aspect of the present disclosure is to provide a multilayer capacitor having high capacitance, reduced ESR and ESL.
According to an aspect of the present disclosure, a multilayer capacitor includes including a capacitor body including first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, fifth and sixth surfaces connected to the first and second surfaces and to the third and fourth surfaces and opposing each other, and including first and second dielectric layers, a plurality of first internal electrodes and a plurality of second internal electrodes alternately layered in a first direction in which the fifth and sixth surfaces oppose each other; a first external electrode disposed on the first surface of the capacitor body and connected to the plurality of first internal electrodes; a second external electrode disposed on the first surface of the capacitor body, spaced apart from the first external electrode, and connected to the plurality of second internal electrodes. Portions of first and second internal electrodes are disposed on a first dielectric layer and are spaced apart from each other. Other portions of first and second internal electrodes are disposed on a second dielectric layer and are spaced apart from each other, and the first and second dielectric layers are alternately layered in the first direction such that the first internal electrode of the first dielectric layer overlaps the second internal electrode of the second dielectric layer in the first direction, and the second internal electrode of the first dielectric layer overlaps the first internal electrode of the second dielectric layer in the first direction.
The first internal electrode may include a 1-1st internal electrode disposed on the first dielectric layer; a 1-2nd internal electrode disposed on the second dielectric layer and configured to not overlap the 1-1st internal electrode in the first direction; a 1-1st connection portion connected to the 1-1st internal electrode and having an end exposed through the first surface of the capacitor body and connected to the first external electrode; and a 1-2nd connection portion connected to the 1-2nd internal electrode and having an end exposed through the first surface of the capacitor body and connected to the first external electrode, and the second internal electrode may include a 2-1st internal electrode disposed on the first dielectric layer and configured to overlap the 1-2nd internal electrode in the first direction; a 2-2nd internal electrode disposed on the second dielectric layer and configured to overlap the 1-1st internal electrode in the first direction; a 2-1st connection portion connected to the 2-1st internal electrode and having an end exposed through the first surface of the capacitor body and connected to the second external electrode; and a 2-2nd connection portion connected to the 2-2nd internal electrode and having an end exposed through the first surface of the capacitor body and connected to the second external electrode.
The 1-1st internal electrode may be symmetrical to the 2-2nd internal electrode in a third direction in which the third and fourth surfaces are connected to each other, and the 1-2nd internal electrode may be symmetrical to the 2-1st internal electrode in the third direction.
The first and second internal electrodes may be spaced apart from the second, third, and fourth surfaces of the capacitor body in the capacitor body.
Each of a combined structure of the 1-2nd internal electrode and the 1-2nd connection portion and a combined structure of the 2-1st internal electrode and the 2-1st connection portion may have a “”-shaped form.
The first internal electrode may include a 1-1st internal electrode disposed on the first dielectric layer; two 1-2nd internal electrodes disposed on the second dielectric layer and configured to not overlap the 1-1st internal electrode in the first direction; a 1-1st connection portion connected to the 1-1st internal electrode and having an end exposed through the first surface of the capacitor body and connected to the first external electrode; and a 1-2nd connection portion connected to the 1-2nd internal electrode and having an end exposed through the first surface of the capacitor body and connected to the first external electrode, and the second internal electrode may include a plurality of 2-1st internal electrodes disposed on the first dielectric layer and configured to overlap the plurality of 1-2nd internal electrodes in the first direction, respectively; a 2-2nd internal electrode disposed on the second dielectric layer and configured to overlap the 1-1st internal electrode in the first direction; a 2-1st connection portion connected to the plurality of 2-1st internal electrodes and having an end exposed through the first surface of the capacitor body and connected to the second external electrode; and a 2-2nd connection portion connected to the 2-2nd internal electrode and having an end exposed through the first surface of the capacitor body and connected to the second external electrode.
The first and second internal electrodes may be spaced apart from the second, third, and fourth surfaces of the capacitor body in the capacitor body.
The first internal electrode may include a plurality of 1-1st internal electrodes disposed on the first dielectric layer and spaced apart from each other in a second direction in which the first surface and the second surface oppose each other; a plurality of 1-2nd internal electrodes disposed on the second dielectric layer and configured to not overlap the plurality of 1-1st internal electrodes in the first direction and to be spaced apart from each other in the second direction; a 1-1st connection portion connected to the plurality of 1-1st internal electrodes and having an end exposed through the first surface of the capacitor body and connected to the first external electrode; and a 1-2nd connection portion connected to the plurality of 1-2nd internal electrodes and having an end exposed through the first surface of the capacitor body and connected to the first external electrode, and the second internal electrode may include a plurality of 2-1st internal electrodes disposed on the first dielectric layer and configured to overlap the plurality of 1-2nd internal electrodes in the first direction, respectively, and to be spaced apart from each other in the second direction; a plurality of 2-2nd internal electrodes disposed on the second dielectric layer and configured to overlap the plurality of 1-1st internal electrodes in the first direction, respectively, and to be spaced apart from each other in the second direction; a 2-1st connection portion connected to the plurality of 2-1st internal electrodes and having an end exposed through the first surface of the capacitor body and connected to the second external electrode; and a 2-2nd connection portion connected to the plurality of 2-2nd internal electrodes and having an end exposed through the first surface of the capacitor body and connected to the second external electrode.
The first and second internal electrodes may be spaced apart from the second, third, and fourth surfaces of the capacitor body in the capacitor body.
According to an aspect of the present disclosure, a board on which a multilayer capacitor is mounted includes a board having first and second electrode pads on one surface; and the multilayer capacitor. The first and second external electrodes are mounted on and connected to the first and second electrode pads, respectively.
According to an aspect of the present disclosure, a multilayer capacitor includes a capacitor body including first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, fifth and sixth surfaces connected to the first and second surfaces and to the third and fourth surfaces and opposing each other, and including first and second dielectric layers alternately layered in a first direction in which the fifth and sixth surfaces oppose each other, the capacitor body further including first and second internal electrodes disposed on each of the first dielectric layers and spaced apart from each other, and third and fourth internal electrodes disposed on each of the second dielectric layers and spaced apart from each other; a first external electrode disposed on the first surface of the capacitor body and connected to each of the first and third internal electrodes; and a second external electrode disposed on the first surface of the capacitor body, spaced apart from the first external electrode, and connected to each of the second and fourth internal electrodes.
Each of the first and second external electrodes may be disposed only on the first surface.
The first internal electrode may overlap the fourth internal electrode in the first direction, and the second internal electrode may overlap the third internal electrode in the first direction.
The first internal electrode may be symmetrical to the fourth internal electrode in a second direction in which the third and fourth surfaces oppose each other, and the third internal electrode may be symmetrical to the second internal electrode in the second direction.
The multilayer capacitor may further include a first connection portion connected to the first internal electrode, and having an end exposed through the first surface of the capacitor body and connected to the first external electrode; a second connection portion connected to the second internal electrode, and having an end exposed through the first surface of the capacitor body and connected to the second external electrode; a third connection portion connected to the third internal electrode, and having an end exposed through the first surface of the capacitor body and connected to the first external electrode; and a fourth connection portion connected to the fourth internal electrode, and having an end exposed through the first surface of the capacitor body and connected to the second external electrode.
Each of the first to fourth internal electrodes and the first to fourth connection portions may be spaced apart from the second, third, and fourth surfaces of the capacitor body.
The multilayer capacitor may further include a fifth internal electrode extending from the second connection portion on the first dielectric layer; and a sixth internal electrode extending from the third connection portion on the second dielectric layer. The fifth internal electrode may overlap the sixth internal electrode in the first direction.
The multilayer capacitor may further include a seventh internal electrode extending from the first connection portion on the first dielectric layer; and an eighth internal electrode extending from the fourth connection portion on the second dielectric layer. The seventh internal electrode may overlap the eighth internal electrode in the first direction.
The first connection portion may overlap the third connection portion in the first direction, and the second connection portion may overlap the fourth connection portion in the first direction.
BRIEF DESCRIPTION OF DRAWINGS
The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a perspective diagram illustrating a multilayer capacitor according to an example embodiment of the present disclosure;
FIG. 2 is a transparent perspective diagram of FIG. 1;
FIGS. 3A and 3B are plan diagrams illustrating first and second dielectric layers and first and second internal electrodes of the multilayer capacitor illustrated in FIG. 1;
FIG. 4 is a perspective diagram illustrating a laminate structure of first and second dielectric layers of the multilayer capacitor illustrated in FIG. 1;
FIG. 5 is a cross-sectional diagram taken along line I-I′ in FIG. 1;
FIG. 6 is a transparent plan diagram of the multilayer capacitor illustrated in FIG. 1;
FIGS. 7A and 7B are plan diagrams illustrating another example embodiment of first and second internal electrodes of a multilayer capacitor;
FIGS. 8A and 8B are plan diagrams illustrating another example embodiment of first and second internal electrodes of a multilayer capacitor;
FIGS. 9A and 9B are plan diagrams illustrating another example embodiment of first and second internal electrodes of a multilayer capacitor; and
FIG. 10 is a cross-sectional diagram illustrating a state in which a multilayer capacitor is mounted on a board.
DETAILED DESCRIPTION
Hereinafter, embodiments of the present disclosure will be described as follows with reference to the attached drawings.
The present disclosure may, however, be exemplified in many different forms and should not be construed as being limited to the specific embodiments set forth herein.
Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Accordingly, shapes and sizes of elements in the drawings may be exaggerated for clarity of description, and elements indicated by the same reference numeral are the same elements in the drawings.
Further, throughout the specification, it will be understood that when a portion “includes” an element, it can further include another element, not excluding another element, unless otherwise indicated.
In the drawings, an X direction, a Y direction, and a Z direction may indicate a length direction, a width direction, and a thickness direction of a capacitor body 110, respectively.
FIG. 1 is a perspective diagram illustrating a multilayer capacitor according to an example embodiment. FIG. 2 is a transparent perspective diagram of FIG. 1. FIGS. 3A and 3B are plan diagrams illustrating first and second dielectric layers and first and second internal electrodes of the multilayer capacitor illustrated in FIG. 1. FIG. 4 is a perspective diagram illustrating a laminate structure of first and second dielectric layers of the multilayer capacitor illustrated in FIG. 1. FIG. 5 is a cross-sectional diagram taken along line I-I′ in FIG. 1. FIG. 6 is a transparent plan diagram of the multilayer capacitor illustrated in FIG. 1.
Referring to FIGS. 1 to 6, a multilayer capacitor 100 in the example embodiment may include a capacitor body 110 and first and second external electrodes 131 and 132.
The capacitor body 110 may be formed by layering a plurality of first and second dielectric layers 111 and 112 in the Z direction and performing a sintering process. A boundary between adjacent first and second dielectric layers 111 and 112 of the capacitor body 110 may be integrated such that it may be difficult to identify the boundary without using a scanning electron microscope (SEM).
The capacitor body 110 may have a hexahedral shape, but an external embodiment thereof is not limited thereto. A shape and a size of the capacitor body 110 and the number of the first and second dielectric layers 111 and 112 may not be limited to the examples illustrated in the diagrams.
In the example embodiment, both surfaces of the capacitor body 110 opposing each other in the Z direction may be defined as first and second surfaces 1 and 2, both surfaces connected to the first and second surfaces 1 and 2 and opposing each other in the X direction may be defined as third and fourth surfaces 3 and 4, and both surfaces connected to the first and second surfaces 1 and 2 and the third and fourth surfaces 3 and 4 and opposing each other in the Y direction may be defined as fifth and sixth surfaces 5 and 6.
The first and second dielectric layers 111 and 112 may include a ceramic material having a high dielectric constant. For example, the first and second dielectric layers 111 and 112 may include barium titanate (BaTiO3) based powder or strontium titanate (SrTiO3) based ceramic powder. However, an example of the material is not limited thereto as along as sufficient capacitance can be obtained therewith.
The first and second dielectric layers 111 and 112 may further include ceramic additives, organic solvents, plasticizers, coupling agents, dispersing agents, and the like, in addition to the ceramic powder.
The ceramic additive may include, for example, a transition metal oxide or a transition metal carbide, a rare earth element, magnesium (Mg) or aluminum (Al), and the like.
The capacitor body 110 may include an active region as a portion contributing to forming capacitance of the capacitor, and cover regions formed on both sides of the active region in the Y direction as margin portions.
The cover regions may have a material and a configuration the same as those of the first and second dielectric layers 111 and 112 other than the configuration in which the cover regions do not include an internal electrode.
The cover regions may be formed by disposing a single dielectric layer or layering two or more dielectric layers on both sides of the active region in the Y direction, and may prevent damage to an internal electrode caused by physical or chemical stress.
The capacitor body 110 may include a plurality of first internal electrodes and a plurality of second internal electrodes.
The first and second internal electrodes may be provided with different polarities, and may be disposed on one surfaces of the first and second dielectric layers 111 and 112 and may be spaced apart from each other.
The first and second internal electrodes may be spaced apart from the second, third, and fourth surfaces 2, 3, and 4 of the capacitor body 110, the first internal electrode may be connected to the first external electrode 131, and the second internal electrode may be connected to the second external electrode 132.
Accordingly, when a certain level of voltage is applied to the first and second external electrodes 131 and 132, an electric charge may be accumulated between the first and second internal electrodes.
Capacitance of the multilayer capacitor 100 may be proportional to an area of overlap between the first and second internal electrodes overlapping in the Y direction in the active region.
A material of the first and second internal electrodes is not limited to any particular material, and may be formed using a conductive paste including one or more materials from among noble materials such as platinum (Pt), palladium (Pd), palladium-silver (Pd—Ag) alloy, and the like, nickel (Ni), and copper (Cu).
As a method of printing the conductive paste, a screen-printing method or a gravure printing method may be used, but an example of the method is not limited thereto.
The first and second external electrodes 131 and 132 may be provided with voltages having different polarities, may be disposed on the first surface 1 of the capacitor body 110 and may be spaced apart from each other in the X direction, and may be electrically connected to the first and second internal electrodes through connection portions exposed through the first surface 1 of the capacitor body 110, respectively.
In the example embodiment, the first and second external electrodes 131 and 132 may only be formed on the first surface 1 of the capacitor body 110.
Accordingly, an overall mounting area of the multilayer capacitor may be relatively reduced as compared to a general structure in which external electrodes are formed on the right and left sides of the capacitor body. Accordingly, mounting density of the board may improve.
The first and second external electrodes 131 and 132 may further include a plating layer configured to cover each of surfaces of the first and second external electrodes 131 and 132.
In the example embodiment, two or more internal electrodes may be disposed on each of the first dielectric layer 111 and the second dielectric layer 112, and the first and second internal electrodes may be spaced apart from each other on the first dielectric layer 111 and also on the second dielectric layer 112.
In other words, the first and second internal electrodes may be spaced apart from each other on a first dielectric layer 111, and the first and second internal electrodes may be spaced apart from each other on a second external electrode 132. In the multilayer capacitor 100, the first and second dielectric layers 111 and 112 may be alternately layered in the Y direction such that the first internal electrode of the first dielectric layer 111 may overlap the second internal electrode of the second dielectric layer 112 in the Y direction, and the second internal electrode of the first dielectric layer 111 may overlap the first internal electrode of the second dielectric layer 112 in the Y direction.
In the example embodiment, the first internal electrode may include a 1-1st internal electrode 121a, a 1-2nd internal electrode 123a, a 1-1st connection portion 121b and a 1-2nd connection portion 123b.
The 1-1st internal electrode 121a may be disposed on the first dielectric layer 111 and may be spaced apart from an edge of the first dielectric layer 111.
The 1-2nd internal electrode 123a may be disposed on the second dielectric layer 112, may be spaced apart from an edge of the second dielectric layer 112, and may be configured to not overlap the 1-1st internal electrode 121a in the Y direction.
The 1-1st connection portion 121b may be a portion extending from an end of the 1-1st internal electrode 121a in the Z direction, and a portion 121c extending downwardly may be exposed to the first surface 1 of the capacitor body 110 and may be connected to the first external electrode 131.
The 1-2nd connection portion 123b may be a portion extending from an end of the 1-2nd internal electrode 123a in the Z direction, and a lower end of the 1-2nd connection portion 123b may be exposed to the first surface 1 of the capacitor body 110 and may be connected to the first external electrode 131.
The 1-1st connection portion 121b and the 1-2nd connection portion 123b may be disposed adjacent to the third surface 3 of the capacitor body 110 to increase an effective area of the internal electrode.
The 1-1st internal electrode 121a may be configured to be adjacent to the downward side of the first dielectric layer 111 in the Z direction, and the 1-2nd internal electrode 123a may be configured to be adjacent to the upward side of the second dielectric layer 112 in the Z direction. Accordingly, when the capacitor body 110 is formed by layering the first and second dielectric layers 111 and 112 in the Y direction, the 1-1st internal electrode 121a and the 1-2nd internal electrode 123a may not overlap each other in the Y direction.
The 1-1st connection portion 121b and the 1-2nd connection portion 123b may be spaced apart from the second, third, and fourth surfaces 2, 3, and 4 of the capacitor body 110.
If desired, the 1-1st connection portion 121b and the 1-2nd connection portion 123b may be configured to be exposed through the third surface 3 of the capacitor body 110, but in this case, the first external electrode may need to be formed on the third surface 3 of the capacitor body 110, or an insulation portion may need to be disposed on the third surface 3 of the capacitor body 110.
Accordingly, a combined structure of the 1-2nd internal electrode 123a and the 1-2nd connection portion 123b may have an “”-shaped form, but an example embodiment thereof is not limited thereto.
The second internal electrode may include a 2-1st internal electrode 122a, a 2-2nd internal electrode 124a, a 2-1st connection portion 122b, and a 2-2nd connection portion 124b.
The 2-1st internal electrode 122a may be disposed on the first dielectric layer 111 and may be spaced apart from an edge of the first dielectric layer 111.
The 2-2nd internal electrode 124a may be disposed on the second dielectric layer 112, may be spaced apart from an edge of the second dielectric layer 112, and may be configured to not overlap the 2-1st internal electrode 122a in the Y direction.
The 2-1st connection portion 122b may be a portion extending from an end of the 2-1st internal electrode 122a in the Z direction, and a lower end of the 2-1st connection portion 122b may be exposed to the first surface 1 of the capacitor body 110 and may be connected to the second external electrode 132.
The 2-2nd connection portion 124b may be a portion extending from an end of the 2-2nd connection portion 124b in the Z direction, and a portion 124c extending downwardly may be exposed to the first surface 1 of the capacitor body 110 and may be connected to the second external electrode 132.
The 2-1st connection portion 122b and the 2-2nd connection portion 124b may be disposed adjacent to the fourth surface 4 of the capacitor body 110 to increase an effective area of the internal electrode.
In other words, the 2-1st internal electrode 122a may be disposed adjacent to the upper side of the first dielectric layer 111 in the Z direction, and the 2-2nd internal electrode 124a may be formed adjacent to the downward side of the second dielectric layer 112 in the Z direction. Accordingly, when the capacitor body 110 is formed by layering the first and second dielectric layers 111 and 112 in the Z direction, the 2-1st internal electrode 122a and the 2-2nd internal electrode 124a may not overlap each other in the Y direction.
The 2-1st connection portion 122b and the 2-2nd connection portion 124b may be spaced apart from the second, third, and fourth surfaces 2, 3, and 4 of the capacitor body 110.
If desired, the 2-1st connection portion 122b and the 2-2nd connection portion 124b may be configured to be exposed through the fourth surface 4 of the capacitor body 110, but in this case, the second external electrode may need to be formed on the fourth surface 4 of the capacitor body 110, or an insulation portion may need to be disposed on the fourth surface 4 of the capacitor body 110.
Accordingly, a combined structure of the 2-1st internal electrode 122a and the 2-1st connection portion 122b may have an “”-shaped form, but an example embodiment thereof is not limited thereto.
The 1-1st internal electrode 121a disposed on the first dielectric layer 111 may be symmetrical to the 2-2nd internal electrode 124a disposed on the second dielectric layer 112 in the X direction, and the 1-2nd internal electrode 123a disposed on the first dielectric layer 111 may be symmetrical to the 2-1st internal electrode 122a disposed on the second dielectric layer 112 in the X direction.
FIGS. 7A and 7B are plan diagrams illustrating another example embodiment of first and second internal electrodes of a multilayer capacitor.
Referring to FIGS. 7A and 7B, the first and second internal electrodes may be spaced apart from the second, third, and fourth surfaces 2, 3, and 4 of the capacitor body 110 in the capacitor body 110.
The first internal electrode may include a 1-1st internal electrode 141 disposed on a first dielectric layer 111 and two 1-2nd internal electrodes 142 and 143 disposed on a second dielectric layer 112 and configured to not overlap the 1-1st internal electrode 141 in the Y direction.
A 1-1st connection portion 142 may be connected to an end of the 1-1st internal electrode 141, and a lower end of the 1-1st connection portion 142 may be exposed through the first surface 1 of the capacitor body 110 and may be connected to a first external electrode 131.
A 1-2nd connection portion 145 may be connected to ends of the two 1-2nd internal electrodes 142 and 143, and a lower end of the 1-2nd connection portion 145 may be exposed through the first surface 1 of the capacitor body 110 and may be connected to the first external electrode 131.
The second internal electrode may include two 2-1st internal electrodes 151 and 152 disposed on the first dielectric layer 111 and configured to overlap the two 1-2nd internal electrodes 143 and 144 in the Y direction, respectively, and a 2-2nd internal electrode 154 disposed on the second dielectric layer 112 and configured to overlap the 1-1st internal electrode 141 in the Y direction.
Also, a 2-1st connection portion 153 may be connected to ends of the two 2-1st internal electrodes 151 and 152, and a lower end of the 2-1st connection portion 153 may be exposed through the first surface 1 of the capacitor body 110 and may be connected to a second external electrode 132.
A 2-2nd connection portion 155 may be connected to an end of the 2-2nd internal electrode 154, and a lower end of the 2-2nd connection portion 155 may be exposed through the first surface 1 of the capacitor body 110 and may be connected to a second electrode 132.
In another example embodiment, the first internal electrode may include a plurality of 1-1st internal electrodes disposed on the first dielectric layer in the second direction in which the first surface and the second surface are connected to each other and spaced apart from each other in the second direction; a plurality of 1-2nd internal electrodes disposed on the second dielectric layer and configured to not overlap the plurality of 1-1st internal electrodes in the first direction and to be spaced apart from each other in the second direction; a 1-1st connection portion connected to the plurality of 1-1st internal electrodes and having an end exposed through the first surface of the capacitor body and connected to the first external electrode; and a 1-2nd connection portion connected to the plurality of 1-2nd internal electrodes and having an end exposed through the first surface of the capacitor body and connected to the first external electrode.
The second internal electrode may include a plurality of 2-1st internal electrodes disposed on the first dielectric layer and configured to overlap the plurality of 1-2nd internal electrodes in the first direction, respectively, and spaced apart from each other in the second direction; a plurality of 2-2nd internal electrodes disposed on the second dielectric layer and configured to overlap the plurality of 1-1st internal electrodes in the first direction, respectively, and to be spaced apart from each other in the second direction; a 2-1st connection portion connected to the plurality of 2-1st internal electrodes and having an end exposed through the first surface of the capacitor body and connected to the second external electrode; and a 2-2 connection portion connected to the plurality of 2-2nd internal electrodes and having an end exposed through the first surface of the capacitor body and connected to the second external electrode.
According to the example embodiment, as the number of current passes of the multilayer capacitor may increase further than the aforementioned example embodiment. Accordingly, directions of electrical fields may be offset from each other such that an inductance element may be reduced, and ESL and ESR of the multilayer capacitor may be reduced.
In the description below, an example embodiment will be described in greater detail.
FIGS. 8A and 8B are plan diagrams illustrating another example embodiment of first and second internal electrodes of a multilayer capacitor.
Referring to FIGS. 8A and 8B, first and second internal electrodes may be spaced apart from the second, third, and fourth surfaces 2, 3, and 4 of a capacitor body 110 in the capacitor body 110.
The first internal electrode may include two 1-1st internal electrodes 161 and 162 disposed on a first dielectric layer 111 and spaced apart from each other in the Z direction, and two 1-2nd internal electrodes 164 and 165 disposed on a second dielectric layer 112 and configured to not overlap the two 1-1st internal electrodes 161 and 162 in the Z direction and to be spaced apart from each other in the Y direction.
A 1-1st connection portion 163 may be connected to ends of the two 1-1st internal electrodes 161 and 162 and an end of the 1-1st connection portion 163 may be exposed through the first surface of the capacitor body and connected to a first external electrode 131.
A 1-2nd connection portion 166 may be connected to ends of the two 1-2nd internal electrodes 164 and 165 and an end of the 1-2nd connection portion 166 may be exposed through the first surface of the capacitor body and connected to the first external electrode 131.
The second internal electrode may include two 2-1st internal electrodes 171 and 172 disposed on the first dielectric layer 111 and configured to overlap the two 1-2nd internal electrodes 164 and 165 in the Y direction, respectively, and to be spaced apart from each other in the Z direction, and two 2-2nd internal electrodes 174 and 175 disposed on the second dielectric layer 112 and configured to overlap the two 1-1st internal electrodes 161 and 162 in the Y direction, respectively, and to be spaced apart from each other in the Z direction.
A 2-1st connection portion 173 may be connected to ends of the two 2-1st internal electrodes 171 and 172, and an end of the 2-1st connection portion 173 may be exposed through the first surface of the capacitor body and connected to a second external electrode 132.
A 2-2nd connection portion 176 may be connected to ends of the two 2-2nd internal electrodes 174 and 175, and an end of the 2-1st connection portion 173 may be exposed through the first surface of the capacitor body and connected to the second external electrode 132.
FIGS. 9A and 9B are plan diagrams illustrating another example embodiment of first and second internal electrodes of a multilayer capacitor.
Referring to FIGS. 9A and 9B, a first internal electrode may include five 1-1st internal electrodes 180 to 184 disposed on a first dielectric layer 111 and spaced apart from each other in the Z direction, and five 1-2nd internal electrodes 185 to 189 disposed on a second dielectric layer 112 and configured to not overlap the five 1-1st internal electrodes 180 to 184 in the Y direction and to be spaced apart from each other in the Z direction.
A 1-1st connection portion 180a may be connected to ends of the five 1-1st internal electrodes 180 to 184, and an end of the 1-1st connection portion 180a may be exposed through the first surface of the capacitor body and connected to a first external electrode 131.
A 1-2nd connection portion 185a may be connected to ends of the five 1-2nd internal electrodes 185 to 189, and an end of the 1-2nd connection portion 185a may be exposed through the first surface of the capacitor body and connected to a first external electrode 131.
The second internal electrode may include five 2-1st internal electrodes 190 to 194 disposed on the first dielectric layer 111, and configured to overlap the five 1-2nd internal electrodes 185 to 189 in the Y direction, respectively, and to be spaced apart from each other in the Z direction, and five 2-2nd internal electrodes 195 to 199 disposed on the second dielectric layer 112 and configured to overlap the five 1-1st internal electrodes 180 to 184 in the Y direction, respectively, and to be spaced apart from each other in the Z direction.
A 2-1st connection portion 190a may be connected to ends of the five 2-1st internal electrodes 190 to 194, and an end of the 2-1st connection portion 190a may be exposed through the first surface of the capacitor body and connected to a second external electrode 132.
A 2-2nd connection portion 195a may be connected to ends of the five 2-2nd internal electrodes 195 to 199, and an end of the 2-2nd connection portion 195a may be exposed through the first surface of the capacitor body and connected to the second external electrode 132.
The multilayer capacitor as configured above may increase a volume of a product as a lower surface electrode structure, and the first and second internal electrodes may overlap in the Y direction and also in the Z direction such that an effective area of the internal electrodes which relates to forming capacitance of the multilayer capacitor may increase. Accordingly, capacitance of the multilayer capacitor may increase.
According to the example embodiment, an effective area of the internal electrodes may increase by 68% approximately as compared to a general multilayer capacitor.
Also, in a conductor in which a current flows, an electrical field may be formed in accordance with a path of a current, and accordingly, an inductance element may be inevitably generated in a direction in which a flow of current is prevented. In a general multilayer capacitor, first and second internal electrodes may be disposed upwardly and downwardly such that a single current path may be implemented.
In the example embodiment, the number of current paths of a multilayer capacitor may greatly increase and directions of currents may be disposed in opposite directions. Accordingly, directions of electrical charges may be offset from each other such that an inductance element may be reduced, and accordingly, ESL and ESR of the multilayer capacitor may be reduced.
Accordingly, the multilayer capacitor of the example embodiment may be applied to various applications requiring relatively low ESL, such as an AP, a smartphone, a laptop, a tablet, a vehicle component, and the like.
If desired, differently from the example embodiment illustrated in the diagrams, in the multilayer capacitor of an example embodiment, the first and second external electrodes may be disposed on the first surface of the capacitor body and may be spaced apart from each other in the Y direction, and the first and second internal electrodes may be configured to rotate in a clockwise direction by 90°.
Referring to FIG. 10, a board on which a multilayer capacitor is mounted may include a board 210 having first and second electrode pads 221 and 222 disposed on one surface, and a multilayer capacitor 100 mounted on an upper surface of the board 210, where first and second external electrodes 131 and 132 may be mounted on and connected to the first and second electrode pads 221 and 222, respectively.
In the example embodiment, the multilayer capacitor 100 may be configured to be mounted on the board 210 by solders 231 and 232, but an example embodiment thereof is not limited thereto. Instead of solder, conductive paste may be used.
According to the aforementioned example embodiment, by disposing an external electrode on a lower surface of the capacitor body, a volume of a product may increase and an effective area of an internal electrode may be controlled such that the multilayer capacitor may have high capacitance and may have reduced ESR and ESL.
While the exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present invention as defined by the appended claims.
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16849588
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samsung electro-mechanics co., ltd.
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USA
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B2
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Utility Patent Grant (with pre-grant publication) issued on or after January 2, 2001.
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Open
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Apr 27th, 2022 09:11AM
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Apr 27th, 2022 09:11AM
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Samsung
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krx:005930
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Samsung
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Apr 26th, 2022 12:00AM
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Aug 28th, 2020 12:00AM
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https://www.uspto.gov?id=US11315733-20220426
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Multilayer ceramic electronic parts with conductive resin
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A multilayer ceramic electronic component includes a ceramic body having a dielectric layer and an internal electrode, an electrode layer connected to the internal electrode, and a conductive resin layer disposed on the electrode layer and including a conductive metal, a metal having a lower melting point than the conductive metal, a conductive carbon, and a base resin. The conductive carbon is included in the conductive resin layer in an amount of 0.5 to 5.0 parts by weight based on 100 parts by weight of the conductive metal.
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11315733
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1. A multilayer ceramic electronic component, comprising:
a ceramic body including a dielectric layer and an internal electrode;
an electrode layer connected to the internal electrode; and
a conductive resin layer disposed on the electrode layer, and including a conductive metal, a metal having a lower melting point than the conductive metal, a conductive carbon, and a base resin,
wherein the conductive carbon is included in the conductive resin layer in an amount of 0.5 to 5.0 parts by weight based on 100 parts by weight of the conductive metal.
2. The multilayer ceramic electronic component of claim 1, wherein the metal having the lower melting point than the conductive metal is tin (Sn).
3. The multilayer ceramic electronic component of claim 2, wherein the tin (Sn) is included in the conductive resin layer in an amount of 10 to 50 parts by weight based on 100 parts by weight of the conductive metal.
4. The multilayer ceramic electronic component of claim 1, wherein the conductive carbon is at least one of graphene, carbon nanotubes, and carbon black.
5. The multilayer ceramic electronic component of claim 4, wherein the conductive carbon is graphene, and a length of a long axis of the graphene of the conductive carbon is 0.2 nm to 10 μm.
6. The multilayer ceramic electronic component of claim 4, wherein the conductive carbon is graphene, and a length of a short axis of the graphene of the conductive carbon is 0.2 nm to 10 μm.
7. The multilayer ceramic electronic component of claim 1, wherein the conductive carbon is provided as at least one conductive carbon disposed in an area of 1 μm×1 μm (width×height) in a cross-section of the conductive resin layer.
8. A multilayer ceramic electronic component, comprising:
a ceramic body including a dielectric layer and an internal electrode;
an electrode layer connected to the internal electrode; and
a conductive resin layer disposed on the electrode layer, and including a conductive metal, a metal having a lower melting point than the conductive metal, a conductive carbon, and a base resin,
wherein the conductive resin layer has a composition having two peaks in Raman analysis thereof.
9. The multilayer ceramic electronic component of claim 8, wherein the composition of the conductive resin layer has the two peaks including a peak in a D band and a peak in a G band.
10. The multilayer ceramic electronic component of claim 8, wherein the conductive carbon is graphene.
11. The multilayer ceramic electronic component of claim 10, wherein the graphene is included in the conductive resin layer in an amount of 0.5 to 5.0 parts by weight based on 100 parts by weight of the conductive metal.
12. The multilayer ceramic electronic component of claim 10, wherein a length of a long axis of the graphene is 0.2 nm to 10 μm.
13. The multilayer ceramic electronic component of claim 10, wherein a length of a short axis of the graphene is 0.2 nm to 10 μm.
14. The multilayer ceramic electronic component of claim 8, wherein the metal having the lower melting point than the conductive metal is tin (Sn).
15. The multilayer ceramic electronic component of claim 14, wherein the tin (Sn) is included in the conductive resin layer in an amount of 10 to 50 parts by weight based on 100 parts by weight of the conductive metal in the conductive resin layer.
16. A multilayer ceramic electronic component, comprising:
a ceramic body including first internal electrodes and second internal electrodes that are alternately stacked with dielectric layers disposed therebetween; and
first and second external electrodes disposed an external surface of the ceramic body and respectively connected to the first and second internal electrodes,
wherein each of the first and second external electrodes includes a conductive resin layer including a conductive metal, a metal having a lower melting point than the conductive metal, a conductive carbon, and a base resin, and
content of the conductive carbon in the conductive resin layer is 0.4 wt % to 5.0 wt %.
17. The multilayer ceramic electronic component of claim 16, wherein the conductive carbon is at least one of graphene and carbon black.
18. The multilayer ceramic electronic component of claim 16, wherein the metal having the lower melting point than the conductive metal is included in the conductive resin layer in an amount of 10 to 50 parts by weight based on 100 parts by weight of the conductive metal in the conductive resin layer.
19. The multilayer ceramic electronic component of claim 16, wherein the first and second external electrodes are disposed on respective opposing surface of the ceramic body, and each include an electrode layer disposed between the conductive resin layer and the respective opposing surface of the ceramic body.
20. The multilayer ceramic electronic component of claim 16, wherein the conductive metal of the conductive resin layer of the first and second external electrodes includes at least one of copper (Cu), nickel (Ni), silver (Ag), and silver-palladium (Ag—Pd).
21. A multilayer ceramic electronic component, comprising:
a ceramic body including a dielectric layer and an internal electrode;
an electrode layer connected to the internal electrode; and
a conductive resin layer disposed on the electrode layer, and including tin (Sn), a conductive metal having a melting point higher than tin (Sn), a base resin, and graphene or carbon black,
wherein the tin (Sn) is included in the conductive resin layer in an amount of 10 to 50 parts by weight based on 100 parts by weight of the conductive metal in the conductive resin layer.
22. The multilayer ceramic electronic component of claim 21, wherein the graphene in the conductive resin layer is 0.5 to 5.0 parts by weight based on 100 parts by weight of the conductive metal.
23. The multilayer ceramic electronic component of claim 21, wherein the carbon black in the conductive resin layer is 0.5 to 5.0 parts by weight based on 100 parts by weight of the conductive metal.
24. The multilayer ceramic electronic component of claim 21, wherein a length of a long axis of the graphene in the conductive resin layer is 0.2 nm to 10 μm.
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CROSS-REFERENCE TO RELATED APPLICATION(S)
This application claims benefit of priority to Korean Patent Application No. 10-2019-0115900 filed on Sep. 20, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
BACKGROUND
1. Field
The present inventive concept relates to a multilayer ceramic electronic component with high bending strength and electrical conductivity.
2. Description of Related Art
A multilayer ceramic capacitor is a type of ceramic electronic component that may include a plurality of dielectric layers, internal electrodes disposed to oppose each other with the dielectric layers interposed therebetween, and external electrodes electrically connected to the internal electrodes.
The internal electrodes and the external electrodes are manufactured using paste containing a conductive metal powder, in general.
A multilayer ceramic capacitor is widely used as a component of a mobile communications device such as a computer, a personal digital assistant (PDA), and a mobile phone due to its small size, high capacity, and ease of mounting.
Meanwhile, with the recent increase in industrial interest in electronic components, multilayer ceramic capacitors also require characteristics of high reliability and high strength to be used in automotive or infotainment systems.
In a multilayer ceramic capacitor, a conductive resin layer is applied to an external electrode to withstand vibrations of a vehicle body, physical shocks, and thermal shocks such as high temperature and high humidity.
A polymer material such as epoxy is applied to the conductive resin layer to improve impact resistance, and a metal powder may be mixed with a polymer material to implement electrical characteristics.
As the metal powder, a single component such as copper (Cu), tin (Sn), nickel (Ni), silver (Ag), or the like, or a mixture are being studied, and the research into Sn, a low melting point metal powder, is being actively conducted.
In recent research, Sn powder, a low melting point metal powder, and Cu powder, a high melting point metal powder, are applied, and a heat-treatment is performed at a temperature equal to or greater than a melting point of Sn to form a Cu—Sn alloy. Thus, interfacial adhesion with an electrode layer disposed there below is improved and electrical conductivity is increased.
However, if the content of Sn is high, due to network formation between Sn, a problem may occur in which the impact resistance of a conductive resin layer may be degraded.
Therefore, even if only a small amount of Sn is included, research is required to improve the interfacial adhesion with a lower electrode layer and to increase the electrical conductivity.
SUMMARY
An aspect of the present inventive concept is to provide a multilayer ceramic electronic component with high bending strength and electrical conductivity.
According to an aspect of the present inventive concept, a multilayer ceramic electronic component includes a ceramic body having a dielectric layer and an internal electrode, an electrode layer connected to the internal electrode, and a conductive resin layer disposed on the electrode layer and including a conductive metal, a metal having a lower melting point than the conductive metal, a conductive carbon, and a base resin. The conductive carbon is included in the conductive resin layer in an amount of 0.5 to 5.0 parts by weight based on 100 parts by weight of the conductive metal.
According to another aspect of the present inventive concept, a multilayer ceramic electronic component includes a ceramic body having a dielectric layer and an internal electrode, an electrode layer connected to the internal electrode, and a conductive resin layer disposed on the electrode layer and including a conductive metal, a metal having a lower melting point than the conductive metal, a conductive carbon, and a base resin. The conductive resin layer has a composition having two peaks in Raman analysis thereof.
According to another aspect of the present inventive concept, a multilayer ceramic electronic component includes a ceramic body having first internal electrodes and second internal electrodes that are alternately stacked with dielectric layers disposed therebetween, and first and second external electrodes disposed an external surface of the ceramic body and respectively connected to the first and second internal electrodes. Each of the first and second external electrodes includes a conductive resin layer including a conductive metal, a metal having a lower melting point than the conductive metal, a conductive carbon, and a base resin, and the content of the conductive carbon in the conductive resin layer is 0.4 wt % to 5.0 wt %.
According to another aspect of the present inventive concept, a multilayer ceramic electronic component includes a ceramic body having a dielectric layer and an internal electrode, an electrode layer connected to the internal electrode, and a conductive resin layer disposed on the electrode layer and including tin (Sn), a conductive metal having a melting point higher than tin (Sn), a base resin, and graphene or carbon black. The tin (Sn) is included in the conductive resin layer in an amount of 10 to 50 parts by weight based on 100 parts by weight of the conductive metal in the conductive resin layer.
BRIEF DESCRIPTION OF DRAWINGS
The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a perspective view illustrating a multilayer ceramic capacitor according to an embodiment of the present disclosure;
FIG. 2 is a cross-sectional view taken along line A-A′ of FIG. 1;
FIG. 3 is an enlarged view of region P of FIG. 2;
FIG. 4 is a schematic enlarged view illustrating graphene, as used in one configuration of the present disclosure;
FIG. 5 is a graph illustrating a nuclear magnetic resonance (NMR) analysis result of external electrode paste including graphene according to an embodiment of the present disclosure;
FIG. 6 is a graph illustrating a Raman analysis result with respect to a conductive resin layer including graphene according to an embodiment of the present disclosure; and
FIG. 7 is a cross-sectional view according to an additional embodiment.
DETAILED DESCRIPTION
Hereinafter, embodiments of the present disclosure will be described as follows with reference to the attached drawings.
The present disclosure may, however, be exemplified in many different forms and should not be construed as being limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Throughout the specification, it will be understood that when an element, such as a layer, region, or wafer (substrate), is referred to as being “on,” “connected to,” or “coupled to” another element, it can be directly “on,” “connected to,” or “coupled to” the other element or other elements intervening therebetween may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element, there may be no elements or layers intervening therebetween. Like numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be apparent that though the terms first, second, third, etc. may be used herein to describe various members, components, regions, layers, and/or sections, these members, components, regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish one member, component, region, layer, or section from another member, component, region, layer, or section. Thus, a first member, component, region, layer, or section discussed below could be termed a second member, component, region, layer, or section without departing from the teachings of the exemplary embodiments.
Spatially relative terms, such as “above,” “upper,” “below,” and “lower” and the like, may be used herein for ease of description to describe one element's positional relationship relative to another element(s) in the orientation shown in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device and figures in use or operation in addition to the orientation depicted in the figures. As such, if the device in the figures is turned over, elements described as “above” or “upper” relative to other elements would then be oriented “below” or “lower” relative to the other elements or features. Thus, the term “above” can encompass both the above and below orientations depending on a particular direction of the device or figures. The device and figures may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.
The terminology used herein describes particular embodiments only, and the present disclosure is not limited thereby. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” and/or “comprising” when used in this specification, specify the presence of stated features, integers, steps, operations, members, elements, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, members, elements, and/or groups thereof.
Hereinafter, embodiments of the present disclosure will be described with reference to schematic views shown in the drawings and illustrating embodiments of the present disclosure. In manufactured devices, for example due to manufacturing techniques and/or tolerances, modifications of the shapes of devices may expected relative to the shapes shown in the drawings. Thus, embodiments of the present disclosure should not be construed as being limited to the particular shapes of regions shown herein, but may more generally be understood to include changes in shape resulting from manufacturing process or tolerances. The following embodiments may also be constituted by one or a combination thereof.
The contents of the present disclosure described below may have a variety of configurations and only illustrative configurations are shown and described herein, but the disclosure is not limited thereto.
Preferred embodiments of the present disclosure will hereinafter be described with reference to the attached drawings.
FIG. 1 is a perspective view illustrating a multilayer ceramic capacitor according to an embodiment of the present disclosure.
FIG. 2 is a cross-sectional view taken along line A-A′ of FIG. 1.
FIG. 3 is an enlarged view of region P of FIG. 2.
Referring to FIGS. 1 to 3, a multilayer ceramic electronic component 100 according to an embodiment of the present disclosure includes a ceramic body 110 including dielectric layers 111 and internal electrodes 121 and 122, electrode layers 131a and 131b connected to the internal electrodes 121 and 122, and conductive resin layers 132a and 132b formed on the electrode layers 131a and 131b and including a conductive metal 32a, a metal 32b having a lower melting point than the conductive metal 32a, a conductive carbon 32c, and a base resin 32d.
In detail, the multilayer ceramic electronic component includes the ceramic body 110 including the dielectric layers 111, first and second internal electrodes 121 and 122 alternately stacked to face each other with the dielectric layers 111 interposed therebetween in the ceramic body 110, a first electrode layer 131a electrically connected to the first internal electrode(s) 121, a second electrode layer 131b electrically connected to the second internal electrode(s) 122, a first conductive resin layer 132a formed on the first electrode layer 131a, and a second conductive resin layer 132b formed on the second electrode layer 131b, while the first conductive resin layer 132a and the second conductive resin layer 132b each include a conductive metal 32a, a metal 32b having a lower melting point than the conductive metal 32a, a conductive carbon 32c, and a base resin 32d.
The first and second conductive resin layers 132a and 132b are formed by applying external electrode paste including a conductive metal 32a, a metal 32b having a lower melting point than the conductive metal 32a, a conductive carbon 32c, and a base resin 32d, while the conductive carbon 32c is included in an amount of 0.5 to 5.0 parts by weight based on 100 parts by weight of the conductive metal 32a.
The metal 32b having a lower melting point than the conductive metal 32a may be tin (Sn), and the tin (Sn) may be included in an amount of 10 to 50 parts by weight based on 100 parts by weight of the conductive metal 32a.
Moreover, the conductive carbon 32c may be at least one of graphene, carbon nanotubes, and carbon black. In particular, the conductive carbon 32c may be graphene.
The metal 32b having a lower melting point than the conductive metal 32a and the conductive carbon 32c will be described later.
The base resin 32d is not particularly limited as long as the bonding properties and shock absorption are provided, and the base resin is mixed with powder of the conductive metal 32a to make paste, and may include, for example, an epoxy resin.
The base resin 32d may be included in an amount of 5 to 30 parts by weight based on 100 parts by weight of the conductive metal.
If the content of the base resin 32d is less than 5 parts by weight, it may be difficult to perform a paste manufacturing operation due to lack of resin, phase stability is lowered to cause phase separation or viscosity change on standing, dispersibility of metals is lowered to reduce a filling rate, and thus a decrease in density may be caused. If the content of the base resin 32d exceeds parts by weight, due to the excessive resin content, the intermetallic contact is lowered to increase specific resistance, and an area of a resin in a surface portion is increased. Thus, when the first and second conductive resin layers 132a and 132b are formed to form a plating layer, the unplating problem may occur.
According to the related art, in a multilayer ceramic capacitor for an electrical device, a conductive resin layer is applied to an external electrode to withstand vibrations of a vehicle body, physical shocks, and thermal shocks such as high temperature and high humidity.
In general, when a conductive resin layer is disposed in an external electrode of a multilayer ceramic capacitor, a conductive resin layer is manufactured to cover the entirety of an electrode layer electrically connected to an internal electrode, so a current flows through a conductive resin layer for electrical conduction with the outside.
The conductive resin layer may be formed by including a conductive metal for securing electrical conductivity and a base resin for shock absorption. When the conductive resin layer includes a base resin, durability against external stimuli, such as warpage of a multilayer ceramic electronic component may be improved.
A polymer material such as an epoxy is applied to the conductive resin layer to improve impact resistance, and metal powder is mixed with a polymer material to implement electrical conductivity characteristics.
As a metal powder, a single component such as Cu, Sn, Ni, Ag, or the like, or a mixture thereof are being studied, and the research on Sn, a low melting point metal powder, is being actively conducted.
In the recent research, Sn powder, which is a metal powder having a low melting point, and Cu powder, which is a metal powder having a high melting point (e.g., higher than the melting point of Sn powder), are applied, and a heat-treatment is performed at a temperature equal to or greater than a melting point of Sn to form a Cu—Sn alloy. Thus, interfacial adhesion with an electrode layer disposed below is improved and electrical conductivity is increased.
However, if the content of Sn is high, due to network formation between Sn, a problem in which the impact resistance of a conductive resin layer may be degraded.
However, according to an embodiment of the present disclosure, the first and second conductive resin layers 132a and 132b each include a conductive metal 32a, a metal 32b having a lower melting point than the conductive metal 32a, a conductive carbon 32c, and a base resin 32d, and the conductive carbon 32c is included in an amount of 0.5 to 5.0 parts by weight based on 100 parts by weight of the conductive metal 32a. Thus, even when only a small amount of Sn is included, bending strength could be improved, and a multilayer ceramic electronic component having high electrical conductivity could be implemented.
That is, the metal 32b having a lower melting point than the conductive metal 32a may be tin (Sn), and the tin (Sn) may be included in an amount of 10 to 50 parts by weight based on 100 parts by weight of the conductive metal 32a.
Moreover, the conductive carbon 32c may be at least one of graphene, carbon nanotubes, and carbon black. In particular, the conductive carbon 32c may be graphene.
In detail, the first and second conductive resin layers 132a and 132b include 0.5 to 5.0 parts by weight of the conductive carbon 32c based on 100 parts by weight of the conductive metal 32a, so the bending strength of the multilayer ceramic capacitor according to an embodiment of the present disclosure is improved, and the electrical conductivity is also increased.
If the content of the conductive carbon 32c is less than 0.5 parts by weight, a multilayer ceramic electronic component with low equivalent series resistance could not be implemented, and, due to network formation between Sn, impact resistance may be degraded.
Meanwhile, if the content of the conductive carbon 32c exceeds 5.0 parts by weight, during formation of a plating layer in an upper portion of the first and second conductive resin layers 132a and 132b, the unplating defect or fixing strength degradation may occur.
When the content of the conductive carbon 32c is represented by the content included in paste of an external electrode, the content of the conductive carbon 32c corresponds to the content of about 0.4 wt % to 5.0 wt %. In this case, if the content of the conductive carbon 32c is less than 0.4 wt %, a multilayer ceramic electronic component with low equivalent series resistance as described above could not be implemented, and impact resistance degradation may occur.
Meanwhile, if the content of the conductive carbon 32c exceeds 5.0 wt %, during formation of a plating layer in an upper portion of the first and second conductive resin layers 132a and 132b, the unplating defect or fixing strength degradation may occur.
In detail, if the content of the conductive carbon 32c exceeds 5.0 wt %, due to a resin shortage phenomenon inside the first and second conductive resin layers 132a and 132b, a viscosity ratio becomes high. Thus, when paste for formation of a conductive resin layer is applied to an exterior of a body, a corner portion of the body becomes thin, so moisture resistance characteristics are degraded, and a problem of reduced reliability may thus occur.
Tin (Sn), a metal 32b having a lower melting point than the conductive metal 32a, is included in an amount of 10 to 50 parts by weight based on 100 parts by weight of the conductive metal 32a, and thus interfacial adhesion between the electrode layers 131a and 131b and the conductive resin layers 132a and 132b is improved, so bending strength could be improved.
If the tin (Sn), the metal 32b having a lower melting point than the conductive metal 32a, is included in an amount less than 10 parts by weight based on 100 parts by weight of the conductive metal 32a, interfacial adhesion between an electrode layer and a conductive resin layer is lowered, so a problem related to bending strength may occur.
Meanwhile, if the tin (Sn), the metal 32b having a lower melting point than the conductive metal 32a, is included in an amount greater than 50 parts by weight based on 100 parts by weight of the conductive metal 32a, due to network formation between Sn, impact resistance degradation may occur.
Referring to FIG. 3, in the conductive resin layers 132a and 132b, the conductive carbon 32c may be provided in the form dispersed in the base resin 32d, and may be adsorbed on a surface of the conductive metal 32a.
Moreover, the conductive carbon 32c may connect the conductive metal 32a to the tin (Sn), the metal 32b having a lower melting point than the conductive metal 32a.
As the conductive carbon 32c connects the conductive metal 32a to the tin (Sn), the metal 32b having a lower melting point than the conductive metal 32a, while interfacial adhesion between the electrode layers 131a and 131b and the conductive resin layers 132a and 132b is improved due to a small amount of tin (Sn), high electrical conductivity is also ensured due to the conductive carbon 32c.
Moreover, the conductive carbon 32c is provided in the form dispersed in the base resin 32d, and thus an increase in equivalent series resistance (ESR) of a multilayer ceramic electronic component due to the base resin 32d may be offset.
In detail, the conductive carbon 32c with excellent electrical conductivity and low specific resistance is dispersed in the base resin 32d for decreasing equivalent series resistance (ESR), and thus the equivalent series resistance (ESR) of the multilayer ceramic electronic component may be lowered.
Meanwhile, the conductive carbon 32c may be graphene. When the conductive carbon 32c is graphene, in the conductive resin layers 132a and 132b, the graphene may be dispersed in a plate shape.
Since the graphene is dispersed in a plate shape inside the first and second conductive resin layers 132a and 132b, a specific surface area is large, so an effect of reduction of equivalent series resistance (ESR) of a multilayer ceramic electronic component may be more excellent.
According to the related art, in order to solve a problem in which the equivalent series resistance (ESR) of a multilayer ceramic electronic component is increased due to a conductive resin layer included in an external electrode, attempts have been made to include carbon nanotubes (CNT) in a conductive resin layer.
The carbon nanotubes (CNT) are manufactured to include at least one between a single-wall carbon nanotube and a multi-wall carbon nanotube.
However, the carbon nanotubes (CNT) have a filled or empty column shape, or a pipe shape having a passage therein. In this regard, if the carbon nanotubes (CNT) are not included in an amount equal to or greater than a certain amount, the effect of a reduction of equivalent series resistance (ESR) of a multilayer ceramic electronic component is not significant.
Moreover, to allow intermetallic contact and tunneling in a conductive resin layer, the dispersion in paste of an external electrode is required.
On the other hand, if the content of carbon nanotubes (CNT) is excessive in order to increase an effect of reduction of equivalent series resistance (ESR) of a multilayer ceramic electronic component, a problem related to dispersion of carbon nanotubes (CNT) in paste of an external electrode may occur.
Moreover, if the content of the carbon nanotubes (CNT) is excessive, during formation of a plating layer in an upper portion of a conductive resin layer, a problem of the unplating defect or fixing strength degradation may occur.
In addition, if the content of the carbon nanotubes (CNT) is excessive, the content of a base resin contained in a conductive resin layer is relatively small, and thus an impact mitigation effect due to the elasticity of the conductive resin layer cannot be obtained.
However, according to an embodiment of the present disclosure, as a conductive carbon 32c in the first and second conductive resin layers 132a and 132b, graphene 32c having a plate shape of which specific surface area is large is included, so an effect of reduction of equivalent series resistance (ESR) of a multilayer ceramic electronic component may be more excellent.
That is, since the graphene 32c according to an embodiment of the present disclosure has a plate shape and a specific surface area thereof is large, as compared with carbon nanotubes, only a small amount of graphene could be used to obtain an excellent effect of reduction of equivalent series resistance (ESR) of a multilayer ceramic electronic component.
Moreover, since a small amount of the graphene 32c has higher electrically-conductive characteristics as compared with carbon nanotubes, the graphene could be uniformly dispersed during manufacturing of paste of an external electrode, so reliability may be excellent.
Moreover, the first and second conductive resin layers 132a and 132b include a content of graphene 32c in a certain range as a conductive carbon, and thus, during formation of a plating layer above, a problem of the unplating defect or fixing strength degradation may not occur.
In addition, even when the first and second conductive resin layers 132a and 132b include a small amount of graphene 32c, an effect of reduction of equivalent series resistance (ESR) of a multilayer ceramic electronic component could be obtained, so the content of a base resin could be included in a manner similar to the related art. Thus, an impact mitigation effect due to the elasticity of the conductive resin layer could be obtained in a manner similar to the related art.
Moreover, as described above, the first and second conductive resin layers 132a and 132b include a conductive metal 32a and tin (Sn), and the metal 32b having a lower melting point than the conductive metal 32a, and the conductive carbon 32c connects the conductive metal 32a and tin (Sn) 32b, so bending strength of a multilayer ceramic capacitor could be improved and high electrical conductivity could be implemented.
As the conductive carbon, a length of a long axis of the graphene 32c is 0.2 nm to 10 μm, and a length of short axis thereof is 0.2 nm to 10 μm, but it is not necessarily limited thereto.
According to an embodiment of the present disclosure, the graphene 32c may be provided as at least one piece of graphene disposed in an area of 1 μm×1 μm (width×height) in the first and second conductive resin layers 132a and 132b. For example, the amount of graphene 32c may be provided in the first and second conductive resin layers 132a and 132b in a sufficient concentration such that at least one piece of graphene is disposed in an area of 1 μm×1 μm (width×height) in a cross-section of the first and second conductive resin layers 132a and 132b.
Measurement of the graphene 32c is not particularly limited, and, for example, the graphene may be measured in an area of 1 μm×1 μm (width×height) in the first and second conductive resin layers 132a and 132b.
For example, regarding measurement of the graphene 32c in an area of 1 μm×1 μm (width×height) in the first and second conductive resin layers 132a and 132b, an image of a cross-section in a length-thickness direction of a multilayer ceramic capacitor is scanned using a transmission electron microscope (TEM) to perform measurement.
In detail, the graphene 32c is measured in an area of 1 μm×1 μm (width×height) for acquisition of a region of the first and second conductive resin layers 132a and 132b extracted from an image, in which a cross-section in a length-thickness (L-T) direction, cut in the center in a width (W) direction of a multilayer ceramic capacitor, is scanned using a transmission electron microscope (TEM).
FIG. 4 is a schematic enlarged view illustrating graphene, as may be used in one configuration of the present disclosure.
Referring to FIG. 4, the graphene 32c may have a form in which a plurality of plate-shaped structures are stacked.
Since a specific surface area of each plate-shaped structure is large, with only a small amount of the graphene 32c having a form in which a plurality of plate-shaped structures are stacked, an effect of reduction of equivalent series resistance (ESR) of a multilayer ceramic electronic component may be excellent.
That is, the graphene 32c with low specific resistance and excellent electrical conductivity has a plate-shaped structure in which a specific surface area is large, and respective plate-shaped structures are stacked as a plurality of plate-shaped structures, and thus, with only a small amount of graphene, an effect of reduction of equivalent series resistance (ESR) of a multilayer ceramic electronic component may be excellent.
In addition, even when the first and second conductive resin layers 132a and 132b include a small amount of graphene 32c, an effect of reduction of equivalent series resistance (ESR) of a multilayer ceramic electronic component could be obtained, so the content of a base resin could be included in a manner similar to the related art. Thus, an impact mitigation effect due to the elasticity of the conductive resin layer could be obtained in a manner similar to the related art.
Moreover, the first and second conductive resin layers 132a and 132b include a conductive metal 32a and a metal 32b such as tin (Sn) having a lower melting point than the conductive metal 32a, and the conductive carbon 32c connects the conductive metal 32a and tin (Sn) 32b, so bending strength of a multilayer ceramic capacitor could be improved and high electrical conductivity could be implemented.
The conductive metal 32a may be one or more selected from the group consisting of copper (Cu), nickel (Ni), silver (Ag), and silver-palladium (Ag—Pd), but it is not limited thereto.
A raw material of the dielectric layer 111 is not particularly limited as long as sufficient capacitance may be obtained. For example, the raw material of the dielectric layer 111 may be barium titanate (BaTiO3) powder particles. Moreover, a material of the dielectric layer 111 may be prepared by adding various ceramic additives, organic solvents, plasticizers, binders, dispersing agents, and the like, to powder particles such as barium titanate (BaTiO3) powder particles, or the like, according to an object of the present disclosure.
Here, a material, forming the first and second internal electrodes 121 and 122, is not particularly limited. For example, the first and second internal electrodes 121 and 122 may include at least one among silver (Ag), lead (Pb), platinum (Pt), nickel (Ni), and copper (Cu).
The first and second electrode layers 131a and 131b are directly connected to the first and second internal electrodes 121 and 122, respectively, to ensure electrical conduction between the first and second external electrodes 130a and 130b and the first and second internal electrodes 121 and 122, respectively.
The first and second electrode layers 131a and 131b may include a conductive metal, and the conductive metal may be nickel (Ni), copper (Cu), palladium (Pd), gold (Au), or alloys thereof, but an embodiment of the present disclosure is not limited thereto.
The first and second electrode layers 131a and 131b may be a sintered electrode formed by sintering paste including a conductive metal.
As described in the embodiment of FIG. 7, plating layers 140a and 140b may be formed on the first and second conductive resin layers 132a and 132b, respectively. The plating layer 140a may include a nickel plating layer 141a and a tin plating layer 142a. Likewise, the plating layer 140b may include a nickel plating layer 141b and a tin plating layer 142b. The nickel plating layers 141a and 141b are disposed on the first and second conductive resin layers 132a and 132b, respectively, while the tin plating layers 142a and 142b may be disposed on the nickel plating layers 141a and 141b, respectively.
Table 1 below shows the results of initial equivalent series resistance (ESR) measurements and a crack incidence rate measurement during evaluation of bending strength, while changing the content of the conductive carbon 32c, based on the content of a conductive metal 32a and a metal 32b having a lower melting point than the conductive metal 32a, included in the first and second conductive resin layers 132a and 132b of a multilayer ceramic capacitor.
The conductive metal 32a was copper (Cu), the metal 32b having a lower melting point than the conductive metal 32a was tin (Sn), and the conductive carbon 32c was graphene.
In Table 1, when a content ratio of copper (Cu):tin (Sn) is 9:1, the case in which graphene is included in an amount of 0 wt % corresponds to Comparative Example 1, because a conductive carbon is not included. Moreover, in this case, Example 1 is a case in which the graphene 32c is included in an amount of 0.1 wt %, Example 2 is a case in which the graphene 32c is included in an amount of 1.0 wt %, and Example 3 is the case in which the graphene 32c is included in an amount of 5.0 wt %.
Next, the case in which a content ratio of copper (Cu):tin (Sn) is 5:5, as the case in which the content of a metal having a lower melting point than a conductive metal based on 100 parts by weight of the conductive metal is 100 parts by weight, corresponds to Comparative Examples 2 to 5.
In the cases of Comparative Examples 2 to 5, graphene is included in the amounts of 0 wt %, 0.1 wt %, 1.0 wt %, and 5.0 wt %, respectively.
A multilayer ceramic capacitor according to each of Comparative Example and Example was manufactured to have a 3216 size (length×width is 3.2 mm×1.6 mm), and Table 1 below shows the results of a crack incidence during evaluation of initial equivalent series resistance (ESR) and bending strength of a multilayer ceramic capacitor.
TABLE 1
0
0.1
1.0
5.0
addition amount of graphene
wt %
wt %
wt %
wt %
content ratio (9:1) of
equivalent series
20
17
8
5
copper(Cu):tin(Sn)
resistance (ESR)
(mΩ)
crack incidence (%)
0
0
0
0
during evaluation of
bending strength
content ratio (5:5) of
equivalent series
5
5
5
5
copper(Cu):tin(Sn)
resistance (ESR)
(mΩ)
crack incidence (%)
80
80
80
80
during evaluation of
bending strength
Referring to Table 1, as the case in which a content ratio of copper (Cu):tin (Sn) is 9:1, in Comparative Example 1 in which graphene is included in an amount of 0 wt %, a value of equivalent series resistance (ESR) of a multilayer ceramic capacitor is high, which may be a problem.
Next, in the case, Comparative Examples 2 to 5, in which a content ratio of copper (Cu):tin (Sn) is 5:5, the content of tin (Sn) is significant, and thus, due to network formation between tin (Sn), it can be seen that a crack incidence is high during evaluation of bending strength.
On the other hand, as the case in which a content ratio of copper (Cu):tin (Sn) is 9:1, in Examples 1 to 3, in which graphene is included in the amounts of 0.1 wt %, 1.0 wt %, and 5.0 wt %, respectively, while a value of equivalent series resistance (ESR) of a multilayer ceramic capacitor was low, cracking did not occur during evaluation of bending strength, so it can be seen that reliability is excellent.
A multilayer ceramic electronic component according to an embodiment of the present disclosure may be manufactured as follows.
First, slurry formed including powder such as barium titanate (BaTiO3) is applied on a carrier film and dried to prepare a plurality of ceramic green sheets, and thus a dielectric layer 111 can be prepared.
Regarding a ceramic green sheet, a ceramic powder, a binder, and a solvent are mixed to prepare slurry, and the slurry is manufactured as a sheet having a thickness of several μm using a doctor blade method.
Next, conductive paste for an internal electrode including nickel powder is prepared.
The conductive paste for an internal electrode is applied on the green sheet using a screen printing method to form an internal electrode, and then a plurality of green sheets on each of which the internal electrode is printed are stacked, and a plurality of green sheets, on which an internal electrode is not printed, are stacked on upper and lower surfaces of a stack structure and then sintered to manufacture a ceramic body 110. The ceramic body includes first and second internal electrodes 121 and 122, dielectric layers 111, and upper and lower cover layers, where the dielectric layer is formed by sintering green sheets on which internal electrodes are printed, and the cover layers are formed by sintering green sheets on which an internal electrode is not printed.
The internal electrodes may be formed as first and second internal electrodes.
First and second electrode layers 131a and 131b may be formed on outer surfaces of a ceramic body 110 to be electrically connected to the first and second internal electrodes 121 and 122, respectively. The first and second electrode layers 131a and 131b may be formed by sintering paste including a conductive metal and glass.
The conductive metal is not particularly limited, but may be one or more selected from the group consisting of copper (Cu), silver (Ag), nickel (Ni), and alloys thereof, and it is preferable to include copper (Cu) as described above.
The glass is not particularly limited, but may be a material having a composition the same as glass used to manufacture an external electrode of a multilayer ceramic capacitor according to the related art.
A conductive resin composition including copper is applied to an exterior of the first and second electrode layers 131a and 131b to form first and second conductive resin layers 132a and 132b. The conductive resin composition may include powder of a conductive metal 32a including copper, tin (Sn) (i.e., a metal 32b having a lower melting point than the conductive metal 32a), and a base resin 32d, and the base resin may be an epoxy resin, a thermosetting resin.
According to an embodiment of the present disclosure, the first and second conductive resin layers 132a and 132b further include a conductive carbon 32c of 0.5 to 5.0 parts by weight based on 100 parts by weight of the conductive metal 32a.
The first and second conductive resin layers 132a and 132b include 0.5 to 5.0 parts by weight of the conductive carbon 32c based on 100 parts by weight of the conductive metal 32a, so equivalent series resistance of a multilayer ceramic capacitor according to an embodiment of the present disclosure may be reduced.
Moreover, the first and second conductive resin layers 132a and 132b include 0.5 to 5.0 parts by weight of the conductive carbon 32c based on 100 parts by weight of the conductive metal 32a, so the bending strength of the multilayer ceramic capacitor according to an embodiment of the present disclosure is improved, and the electrical conductivity is also increased.
In addition, the first and second conductive resin layers 132a and 132b may include 10 to 50 parts by weight of tin (Sn) (i.e., the metal 32b having a lower melting point than the conductive metal 32a), based on 100 parts by weight of the conductive metal 32a.
Tin (Sn), a metal 32b having a lower melting point than the conductive metal 32a, is included in an amount of 10 to 50 parts by weight based on 100 parts by weight of the conductive metal 32a, and thus interfacial adhesion between the electrode layers 131a and 131b and the conductive resin layers 132a and 132b is improved, so bending strength could be improved.
After formation of the first and second conductive resin layers 132a and 132b, further forming of a nickel plating layer and a tin plating layer thereon may be included.
FIG. 5 is a graph illustrating a nuclear magnetic resonance (NMR) analysis result of external electrode paste including graphene according to an embodiment of the present disclosure.
Referring to FIG. 5, when nuclear magnetic resonance (NMR) analysis is performed on paste of an external electrode including graphene according to an embodiment of the present disclosure, it can be seen that a peak due to an sp2 carbon is detected.
The peak a due to the sp2 carbon could be detected in the same manner when analysis is performed on an external electrode of a multilayer ceramic capacitor to which paste of an external electrode including graphene according to an embodiment of the present disclosure is applied.
FIG. 6 is a graph illustrating a Raman analysis result with respect to a conductive resin layer including graphene according to an embodiment of the present disclosure.
Referring to FIG. 6, a multilayer ceramic electronic component 100 according to another embodiment of the present disclosure includes a ceramic body 110 including a dielectric layer 111 and internal electrodes 121 and 122, electrode layers 131a and 131b respectively connected to the internal electrodes 121 and 122, and conductive resin layers 132a and 132b respectively formed on the electrode layers 131a and 131b and including a conductive metal, a metal having a lower melting point than the conductive metal, a conductive carbon, and a base resin, and two peaks are detected, in the Raman analysis of the conductive resin layers 132a and 132b.
As illustrated in a Raman analysis graph of FIG. 6, in the case of Examples 1 to 3, as a sample of an embodiment of the present disclosure, two peaks are detected. In the case of Comparative Example 1, as a Raman analysis graph of graphite, only one peak is detected.
In another embodiment of the present disclosure, the two peaks are detected in a D band and a G band.
Moreover, in the case of Comparative Example 1, the only one peak that is detected is in a G band.
In another embodiment of the present disclosure, the conductive resin layers 132a and 132b include graphene as a conductive carbon.
In the Raman analysis of the conductive resin layers 132a and 132b, two peaks are detected because the conductive resin layers 132a and 132b include graphene, and a Raman analysis graph may be different with another carbon material.
As set forth above, according to example embodiments of the present inventive concept, a conductive resin layer of an external electrode includes a conductive metal, a metal having a lower melting point than the conductive metal, a conductive carbon, and a base resin, and the contents of the metal having a lower melting point than the conductive metal and the conductive carbon are adjusted, so bending strength may be improved, and a multilayer ceramic electronic component having high electrical conductivity may be implemented.
While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present disclosure, as defined by the appended claims.
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17005775
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samsung electro-mechanics co., ltd.
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USA
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B2
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Utility Patent Grant (with pre-grant publication) issued on or after January 2, 2001.
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Open
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Apr 27th, 2022 09:11AM
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Apr 27th, 2022 09:11AM
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Samsung
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krx:005930
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Samsung
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Apr 26th, 2022 12:00AM
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May 29th, 2020 12:00AM
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https://www.uspto.gov?id=US11315729-20220426
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Multilayer ceramic capacitor
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A multilayer ceramic capacitor includes a ceramic body including first and second surfaces opposing each other, and third and fourth surfaces connecting the first and second surfaces, a plurality of internal electrodes disposed inside the ceramic body, exposed from the first and second surfaces, and having an end exposed from the third surface or the fourth surface, and a first side margin and a second side margin respectively disposed on the first and second surfaces, from which end portions of the plurality of internal electrodes are exposed. The first and second side margins include a base material powder of a barium titanate-based base powder and a subcomponent. The subcomponent includes terbium (Tb) as a first subcomponent including a lanthanide rare earth element, and a content ratio of the terbium (Tb) to a content of the first subcomponent (RE) excluding the terbium (Tb) satisfies 0.110≤Tb/RE≤2.333.
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11315729
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1. A multilayer ceramic capacitor comprising:
a ceramic body including first and second surfaces opposing each other, and third and fourth surfaces connecting the first and second surfaces;
a plurality of internal electrodes disposed inside the ceramic body, exposed from the first and second surfaces, and having an end exposed from the third surface or the fourth surface; and
a first side margin and a second side margin respectively disposed on the first and second surfaces, from which end portions of the plurality of internal electrodes are exposed,
wherein the first and second side margins include a barium titanate-based base material, and a subcomponent,
wherein the subcomponent includes terbium (Tb) as a first subcomponent including a lanthanide rare earth element, and a content ratio of the terbium (Tb) to a content of the first subcomponent (RE) excluding the terbium (Tb) satisfies 0.110≤Tb/RE≤2.333
wherein the subcomponent further comprises:
magnesium (Mg) and barium (Ba);
a second subcomponent including a carbonate or an oxide comprising magnesium (Mg); and
a third subcomponent having a content greater than 0.0 and less than 4.5 mol containing at least one of an oxide or carbonate comprising at least one of silicon (Si), barium (Ba) or aluminum (Al), or a glass compound comprising Si, with respect to 100 mol of the barium titanate-based base material, and
wherein a content ratio of the magnesium (Mg) to the total content of the barium (Ba) and silicon (Si) satisfies 0.09≤Mg/(Ba+Si)≤0.19.
2. The multilayer ceramic capacitor of claim 1, wherein a content of the terbium (Tb) satisfies 0.15 mol≤Tb≤1.35 mol with respect to 100 mol of the barium titanate-based base material.
3. The multilayer ceramic capacitor of claim 1, wherein a content ratio of magnesium (Mg) to a content of barium (Ba) of the subcomponent satisfies 0.125≤Mg/Ba≤0.500.
4. The multilayer ceramic capacitor of claim 1, wherein the content of magnesium (Mg) satisfies 0.25 mol≤Mg≤1.0 mol with respect to 100 mol of the barium titanate-based base material.
5. The multilayer ceramic capacitor of claim 1, wherein the content of barium (Ba) of the subcomponent satisfies 0.5 mol≤Ba≤3.0 mol with respect to 100 mol of the barium titanate-based base material.
6. The multilayer ceramic capacitor of claim 1, wherein the subcomponent comprises the first subcomponent in an amount greater than 0.0 and 4.0 mol or less with respect to 100 mol of the barium titanate-based base material powder, the first subcomponent being an oxide or carbonate including at least one of yttrium (Y), dysprosium (Dy), holmium (Ho), erbium (Er), gadolinium (Gd), cerium (Ce), neodymium (Nd), samarium (Sm), lanthanum (La), ytterbium (Yb) or praseodymium (Pr).
7. The multilayer ceramic capacitor of claim 1, wherein a dielectric composition included in the first and second side margins and a dielectric composition included in the ceramic body are different.
8. A multilayer ceramic capacitor comprising:
a ceramic body including first and second surfaces opposing each other, and third and fourth surfaces connecting the first and second surfaces;
a plurality of internal electrodes disposed inside the ceramic body, exposed from the first and second surfaces, and each having an end exposed from the third surface or the fourth surface; and
a first side margin and a second side margin respectively disposed on the first and second surfaces, from which end portions of the plurality of internal electrodes are exposed,
wherein the first and second side margins include a barium titanate-based base material, and a subcomponent,
wherein the subcomponent includes terbium (Tb) as a first subcomponent including a lanthanide rare earth element,
wherein a content ratio of the terbium (Tb) to a content of the first subcomponent (RE) excluding the terbium (Tb) satisfies 0.110≤Tb/RE≤2.333, and
wherein a content ratio of the terbium (Tb) included in the first and second side margins to a content of the barium titanate-based base material included in the first and second side margins, is greater than a content ratio of terbium (Tb) included in the ceramic body to a content of a barium titanate-based base material included in the ceramic body.
9. The multilayer ceramic capacitor of claim 8, wherein the content of terbium (Tb) included in the first and second side margin satisfies 0.15 mol ≤Tb≤1.35 mol with respect to 100 mol of the barium titanate-based base material included in the first and second side margins.
10. The multilayer ceramic capacitor of claim 8, wherein the subcomponent further comprises magnesium (Mg) and barium (Ba), and a content ratio of magnesium (Mg) to a content of barium (Ba) in the subcomponent satisfies 0.125≤Mg/Ba≤0.500.
11. The multilayer ceramic capacitor of claim 10, wherein the content of magnesium (Mg) satisfies 0.25 mol≤Mg≤1.0 mol with respect to 100 mol of the barium titanate-based base material included in the first and second side margins.
12. The multilayer ceramic capacitor of claim 10, wherein the content of barium (Ba) satisfies 0.5 mol≤Ba≤3.0 mol with respect to 100 mol of the barium titanate-based base material included in the first and second side margins.
13. The multilayer ceramic capacitor of claim 10, wherein the subcomponent further comprises:
a second subcomponent including an oxide or carbonate comprising the Mg; and
a third subcomponent having a content greater than 0.0 and less than 4.5 mol containing at least one of an oxide or carbonate comprising at least one of silicon (Si), barium (Ba) or aluminum (Al), or a glass compound comprising Si, with respect to 100 mol of the barium titanate-based base material included in the first and second side margins,
wherein a content ratio of the magnesium (Mg) to a total content of the barium (Ba) and silicon (Si) satisfies 0.09≤Mg/(Ba+Si)≤0.19.
14. The multilayer ceramic capacitor of claim 8, wherein the subcomponent comprises the first subcomponent in an amount greater than 0.0 and 4.0 mol or less with respect to 100 mol of the barium titanate-based base material included in the first and second side margins, the first subcomponent being an oxide or carbonate including at least one of Y, Dy, Ho, Er, Gd, Ce, Nd, Sm, La, Yb or Pr.
15. A multilayer ceramic capacitor comprising:
a ceramic body including first and second surfaces opposing each other, and third and fourth surfaces connecting the first and second surfaces;
a plurality of internal electrodes disposed inside the ceramic body, exposed from the first and second surfaces, and each having an end exposed from the third surface or the fourth surface; and
a first side margin and a second side margin respectively disposed on the first and second surfaces, from which end portions of the plurality of internal electrodes are exposed,
wherein the first and second side margins include a barium titanate-based base material and a subcomponent,
wherein the subcomponent includes terbium (Tb) and one or more other lanthanide rare earth elements as a first subcomponent,
wherein a content ratio of the terbium (Tb) included in the first and second side margins to a content of the barium titanate-based base material included in the first and second side margins, is greater than a content ratio of terbium (Tb) included in the ceramic body to a content of a barium titanate-based base material included in the ceramic body, and
wherein a content of the terbium (Tb) satisfies 0.15 mol≤Tb≤1.35 mol with respect to 100 mol of the barium titanate-based base material included in the first and second side margins.
16. The multilayer ceramic capacitor of claim 15, wherein the subcomponent further comprises magnesium (Mg) and barium (Ba), and a content ratio of magnesium (Mg) to a content of barium (Ba) in the subcomponent satisfies 0.125≤Mg/Ba≤0.500.
17. The multilayer ceramic capacitor of claim 16, wherein the content of magnesium (Mg) satisfies 0.25 mol≤Mg≤1.0 mol with respect to 100 mol of the barium titanate-based base material included in the first and second side margins.
18. The multilayer ceramic capacitor of claim 16, wherein the content of barium (Ba) satisfies 0.5 mol≤Ba≤3.0 mol with respect to 100 mol of the barium titanate-based base material included in the first and second side margins.
19. The multilayer ceramic capacitor of claim 16, wherein the subcomponent further comprises:
a second subcomponent including an oxide or carbonate comprising the Mg; and
a third subcomponent having a content greater than 0.0 and less than 4.5 mol containing at least one of an oxide or carbonate comprising at least one of silicon (Si), barium (Ba) or aluminum (Al), or a glass compound comprising Si, with respect to 100 mol of the barium titanate-based base material included in the first and second side margins,
wherein a content ratio of the magnesium (Mg) to a total content of the barium (Ba) and silicon (Si) satisfies 0.09≤Mg/(Ba+Si)≤0.19.
20. The multilayer ceramic capacitor of claim 15, wherein the subcomponent comprises the first subcomponent in an amount greater than 0.0 and 4.0 mol or less with respect to 100 mol of the barium titanate-based base material included in the first and second side margins, the first subcomponent being an oxide or carbonate including at least one of Y, Dy, Ho, Er, Gd, Ce, Nd, Sm, La, Yb or Pr.
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20
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CROSS-REFERENCE TO RELATED APPLICATION(S)
This application claims benefit of priority to Korean Patent Application No. 10-2019-0142465 filed on Nov. 8, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
TECHNICAL FIELD
The present disclosure relates to a multilayer ceramic capacitor and a method of manufacturing the same, and more particularly, to a multilayer ceramic capacitor in which mechanical strength may be improved and high temperature and moisture resistance may be improved, and a method of manufacturing the same.
BACKGROUND
In general, electronic components using a ceramic material, such as capacitors, inductors, piezoelectric elements, varistors, or thermistors, include a ceramic body formed of a ceramic material, an internal electrode formed inside the body, and an external electrode installed on the surface of the ceramic body to be connected to the internal electrode.
Recently, as electronic products have become miniaturized and multifunctional, chip components are also miniaturized and highly functionalized, and thus, high capacity products, for example, multilayer ceramic capacitors having small sizes and high capacities, are required.
For miniaturization and high capacitance of multilayer ceramic capacitors, it is necessary to secure a dielectric material having good dielectric properties and excellent withstand voltage characteristics.
In addition, thinning of a dielectric and a significant increase in an electrode effective area (increasing the effective volume fraction required for capacity implementation) are required.
However, a local reduction in dielectric thickness may occur due to the thinning of the dielectric and the marginal step difference, and thus, a structural design change to significantly reduce a withstand voltage drop phenomenon occurring due to such a local reduction is essential.
To implement a small-sized and high capacity multilayer ceramic capacitor as described above and to prevent a withstand voltage drop phenomenon, in manufacturing a multilayer ceramic capacitor, there is a method in which the internal electrode is exposed in the width direction of the body, thereby significantly increasing the internal electrode area in the width direction through a marginless design, and a separate margin portion is attached to the electrode exposed surface of the chip in the width direction, in the operation before firing after chip fabrication as above.
However, when the multilayer ceramic capacitor is manufactured as described above, the dielectric composition of the ceramic body is used as is without differentiating the dielectric composition of the side margin from the dielectric composition of the ceramic body.
Therefore, there is a problem in which the interface gap between the electrode end portion and the margin portion join surface is not filled, the interface gap being inevitably generated due to the problem of lowering the densification of the side margin and the sintering drive mismatching phenomenon of the dielectric of the side margin and the internal electrode during the sintering process.
In addition, since in the related art, a ceramic dielectric sheet that acts as a margin is attached to a green chip cut without a margin, by physical compression, and then a sintered body having a rigid body is formed through a high temperature heat treatment. Thus, in this case, when the adhesive force between the electrode exposed surface and the sheet for forming a margin portion in the operation before sintering is insufficient, poor appearance due to removal of margin and serious defects leading to interfacial cracks may occur.
In addition, voids are generated between the electrode end and the margin interface when the volume change occurs inside the chip due to shrinkage of the internal electrode during high temperature heat treatment, acting as a starting point of crack generation or as a moisture penetration path, thereby causing a decrease in moisture resistance reliability.
In addition, to solve the above problems, when the material with high sintering driving force is applied as a general method, the aggregation of an outermost internal electrode near the interface due to excessive grain growth is intensified, resulting in increasing a drop in withstand voltage due to the electrode and dielectric layer unevenness.
Therefore, the dielectric of the margin region should have an excellent sintering driving force, so that the same sintered-body density as that of the ceramic body may be ensured, even with a low physical filling density, thereby significantly reducing the decrease in the strength of the multilayer ceramic capacitor.
In addition, the dielectric used in the margin region should be able to more actively move the material at a high temperature to fill the interface void.
In addition, the interface bonding force should be improved by forming an oxide layer on the end joining surface by reaction with the internal electrode.
SUMMARY
This Summary is provided to introduce a selection of concepts in simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
An aspect of the present disclosure is to provide a high capacity multilayer ceramic capacitor in which mechanical strength and high temperature and moisture resistance may be improved, and a method of manufacturing the same.
According to an aspect of the present disclosure, a multilayer ceramic capacitor includes a ceramic body including first and second surfaces opposing each other, and third and fourth surfaces connecting the first and second surfaces, a plurality of internal electrodes disposed inside the ceramic body, exposed from the first and second surfaces, and having an end exposed from the third surface or the fourth surface, and a first side margin and a second side margin respectively disposed on the first and second surfaces, from which end portions of the plurality of internal electrodes are exposed. The first and second side margins include a base material powder of a barium titanate-based base powder and a subcomponent. The subcomponent includes terbium (Tb) as a first subcomponent including a lanthanide rare earth element, and a content ratio of the terbium (Tb) to a content of the first subcomponent (RE) excluding the terbium (Tb) satisfies 0.110≤Tb/RE≤2.333.
According to an aspect of the present disclosure, a multilayer ceramic capacitor includes a ceramic body including first and second surfaces opposing each other, and third and fourth surfaces connecting the first and second surfaces, a plurality of internal electrodes disposed inside the ceramic body, exposed from the first and second surfaces, and having an end exposed from the third surface or the fourth surface, and a first side margin and a second side margin respectively disposed on the first and second surfaces, from which end portions of the plurality of internal electrodes are exposed. The first and second side margins include a base material powder of a barium titanate-based base powder and a subcomponent. The subcomponent includes terbium (Tb) as a first subcomponent including a lanthanide rare earth element. A content ratio of the terbium (Tb) to a content of the first subcomponent (RE) excluding the terbium (Tb) satisfies 0.110≤Tb/RE≤2.333. A dielectric composition included in the first and second side margins and a dielectric composition included in the ceramic body are different from each other, and a content of the terbium (Tb) included in the first and second side margins is more than a content of terbium (Tb) included in the ceramic body. A content ratio of the terbium (Tb) included in the first and second side margins to a content of the base material powder included in the first and second side margins, is greater than a content ratio of terbium (Tb) included in the ceramic body to a content of a barium titanate-based base powder included in the ceramic body
According to an aspect of the present disclosure, a multilayer ceramic capacitor includes a ceramic body including first and second surfaces opposing each other, and third and fourth surfaces connecting the first and second surfaces, a plurality of internal electrodes disposed inside the ceramic body, exposed from the first and second surfaces, and each having an end exposed from the third surface or the fourth surface, and a first side margin and a second side margin respectively disposed on the first and second surfaces, from which end portions of the plurality of internal electrodes are exposed. The first and second side margins include a base material powder of a barium titanate-based base powder and a subcomponent. The subcomponent includes terbium (Tb) and one or more other lanthanide rare earth elements as a first subcomponent. A content ratio of the terbium (Tb) included in the first and second side margins to a content of the base material powder included in the first and second side margins, is greater than a content ratio of terbium (Tb) included in the ceramic body to a content of a barium titanate-based base powder included in the ceramic body. A content of the terbium (Tb) satisfies 0.15 mol≤Tb≤1.35 mol with respect to 100 mol of the base material powder included in the first and second side margins.
BRIEF DESCRIPTION OF DRAWINGS
The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a schematic perspective view illustrating a multilayer ceramic capacitor according to an embodiment;
FIG. 2 is a cross-sectional view taken along line I-I′ of FIG. 1;
FIG. 3 is a cross-sectional view taken along line II-II′ of FIG. 1;
FIG. 4 is a top plan view illustrating one dielectric layer constituting the multilayer ceramic capacitor illustrated in FIG. 1; and
FIGS. 5A to 5F are cross-sectional views and perspective views schematically illustrating a method of manufacturing a multilayer ceramic capacitor according to another embodiment.
DETAILED DESCRIPTION
The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent to one of ordinary skill in the art. The sequences of operations described herein are merely examples, and are not limited to those set forth herein, but may be changed as will be apparent to one of ordinary skill in the art, with the exception of operations necessarily occurring in a certain order. Also, descriptions of functions and constructions that would be well known to one of ordinary skill in the art may be omitted for increased clarity and conciseness.
The features described herein may be embodied in different forms, and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to one of ordinary skill in the art.
Herein, it is noted that use of the term “may” with respect to an example or embodiment, e.g., as to what an example or embodiment may include or implement, means that at least one example or embodiment exists in which such a feature is included or implemented while all examples and embodiments are not limited thereto.
Throughout the specification, when an element, such as a layer, region, or substrate, is described as being “on,” “connected to,” or “coupled to” another element, it may be directly “on,” “connected to,” or “coupled to” the other element, or there may be one or more other elements intervening therebetween. In contrast, when an element is described as being “directly on,” “directly connected to,” or “directly coupled to” another element, there may be no other elements intervening therebetween.
As used herein, the term “and/or” includes any one and any combination of any two or more of the associated listed items.
Although terms such as “first,” “second,” and “third” may be used herein to describe various members, components, regions, layers, or sections, these members, components, regions, layers, or sections are not to be limited by these terms. Rather, these terms are only used to distinguish one member, component, region, layer, or section from another member, component, region, layer, or section. Thus, a first member, component, region, layer, or section referred to in examples described herein may also be referred to as a second member, component, region, layer, or section without departing from the teachings of the examples.
Spatially relative terms such as “above,” “upper,” “below,” and “lower” may be used herein for ease of description to describe one element's relationship to another element as illustrated in the figures. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as being “above” or “upper” relative to another element will then be “below” or “lower” relative to the other element. Thus, the term “above” encompasses both the above and below orientations depending on the spatial orientation of the device. The device may also be oriented in other ways (for example, rotated 90 degrees or at other orientations), and the spatially relative terms used herein are to be interpreted accordingly.
The terminology used herein is for describing various examples only, and is not to be used to limit the disclosure. The articles “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises,” “includes,” and “has” specify the presence of stated features, numbers, operations, members, elements, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, members, elements, and/or combinations thereof.
Due to manufacturing techniques and/or tolerances, variations of the shapes illustrated in the drawings may occur. Thus, the examples described herein are not limited to the specific shapes illustrated in the drawings, but include changes in shape that occur during manufacturing.
The features of the examples described herein may be combined in various ways as will be apparent after an understanding of the disclosure of this application. Further, although the examples described herein have a variety of configurations, other configurations are possible as will be apparent after an understanding of the disclosure of this application.
The drawings may not be to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience.
Subsequently, examples are described in further detail with reference to the accompanying drawings.
FIG. 1 is a schematic perspective view illustrating a multilayer ceramic capacitor according to an embodiment.
FIG. 2 is a cross-sectional view taken along line I-I′ of FIG. 1.
FIG. 3 is a cross-sectional view taken along line II-II′ of FIG. 1.
FIG. 4 is a top plan view illustrating one dielectric layer constituting the multilayer ceramic capacitor illustrated in FIG. 1.
FIGS. 5A to 5F are cross-sectional views and perspective views schematically illustrating a method of manufacturing a multilayer ceramic capacitor according to another embodiment.
Referring to FIGS. 1 to 4, a multilayer ceramic capacitor according to an embodiment includes a ceramic body 110, a plurality of internal electrodes 121 and 122 formed in the ceramic body 110, and external electrodes 131 and 132 formed on external surfaces of the ceramic body 110.
The ceramic body 110 has a first surface 1 and a second surface 2 opposing each other, and a third surface 3 and a fourth surface 4 connecting the first and second surfaces to each other, and a fifth surface 5 and a sixth surface 6, which are an upper surface and a lower surface.
The first surface 1 and the second surface 2 may be defined as surfaces opposing each other in the width direction (W direction) of the ceramic body 110, while the third surface 3 and the fourth surface 4 may be defined as surfaces opposing each other in the length direction (X direction). The fifth surface 5 and the sixth surface 6 may be defined as surfaces opposing in the thickness direction (Z direction).
The shape of the ceramic body 110 is not particularly limited, but may be a rectangular parallelepiped shape as illustrated in the drawings.
Ends of the plurality of internal electrodes 121 and 122 formed in the ceramic body 110 are exposed to the third surface 3 or the fourth surface 4 of the ceramic body.
The internal electrodes (121 and 122) may be provided as a pair of first internal electrode 121 and second internal electrode 122 having different polarities.
One end of the first internal electrode 121 may be exposed to the third surface 3, and one end of the second internal electrode 122 may be exposed to the fourth surface 4.
The other ends of the first internal electrode 121 and the second internal electrode 122 are formed at a predetermined distance from the third surface 3 or the fourth surface 4, which will be described in more detail later.
First and second external electrodes 131 and 132 may be formed on the third surface 3 and the fourth surface 4 of the ceramic body to be electrically connected to the internal electrodes.
The multilayer ceramic capacitor according to an embodiment includes the plurality of internal electrodes 121 and 122 disposed inside the ceramic body 110, exposed to the first and second surfaces 1 and 2 and having one end to the third surface 3 or the fourth surface, and a first side margin 113 and a second side margin 114 disposed on the end portions of the internal electrodes 121 and 122 exposed to the first surface 1 and the second surface 2.
The plurality of internal electrodes 121 and 122 are formed in the ceramic body 110, and respective ends of the plurality of internal electrodes 121 and 122 are exposed to the first surface 1 and the second surface 2, which are the surfaces of the ceramic body 110 in the width direction. The first side margin 113 and the second side margin 114 are disposed on the exposed end portions, respectively.
A thickness d1 of the first side margin 113 and a thickness d1 of the second side margin 114 may be 18 μm or less.
According to an embodiment, the ceramic body 110 may be comprised of a laminate 111 in which a plurality of dielectric layers 112 are laminated, and the first side margin portion 113 and the second side margin 114 formed on both sides of the laminate.
The plurality of dielectric layers 112 constituting the laminate 111 are in a sintered state and may be integrated so that boundaries between adjacent dielectric layers cannot be identified.
The length of the laminate 111 corresponds to the length of the ceramic body 110, the length of the ceramic body 110 corresponds to the distance from the third surface 3 to the fourth surface 4 of the ceramic body 110. For example, the third and fourth surfaces 3 and 5 of the ceramic body 110 may be understood as the third and fourth surfaces of the laminate 111.
The laminate 111 is formed by stacking the plurality of dielectric layers 112, and the length of the dielectric layer 112 forms a distance between the third surface 3 and the fourth surface 4 of the ceramic body.
Although not particularly limited, according to an embodiment, the length of the ceramic body may be 400 to 1400 μm. In more detail, the length of the ceramic body may be 400 to 800 μm or 600 to 1400 μm.
The internal electrodes 121 and 122 may be formed on the dielectric layers, and the internal electrodes 121 and 122 may be formed in the ceramic body 110 with one dielectric layer 112 interposed therebetween by sintering.
Referring to FIG. 4, the first internal electrode 121 is formed on the dielectric layer 112. The first internal electrode 121 is not entirely formed in the length direction of the dielectric layer. For example, one end of the first internal electrode 121 may be formed at a predetermined distance d2 from the fourth surface 4 of the ceramic body 110, and the other end of the first internal electrode 121 may be formed on the third surface 3, to be exposed to the third surface 3.
The other end of the first internal electrode exposed to the third surface 3 of the laminate is connected to the first external electrode 131.
In contrast to the first internal electrode, one end of the second internal electrode 122 is formed at a predetermined distance from the third surface 3, and the other end of the second internal electrode 122 is exposed to the fourth surface 4 to be connected to the second external electrode 132.
The dielectric layer 112 may have the same width as that of the first internal electrode 121. For example, the first internal electrode 121 may be formed as a whole in the width direction of the dielectric layer 112.
Although not particularly limited, according to an embodiment, the width of the dielectric layer and the width of the internal electrode may be 100 to 900 μm. In more detail, the width of the dielectric layer and the width of the internal electrode may be 100 to 500 μm or 100 to 900 μm.
As the ceramic body becomes smaller, the thickness of the side margin may affect the electrical characteristics of the multilayer ceramic capacitor. According to an embodiment, the side margin may have a thickness of 18 μm or less, thereby improving characteristics of the miniaturized multilayer ceramic capacitor.
In an embodiment, the internal electrode and the dielectric layer are formed by being cut at the same time, and the width of the internal electrode and the width of the dielectric layer may be the same as each other. More details with regard thereto will be described later.
In this embodiment, the width of the dielectric layer is formed to be the same as that of the internal electrode, and thus the ends of the internal electrodes 121 and 122 may be exposed to the first and second surfaces of the ceramic body 110 in the width direction.
The first side margin 113 and the second side margin 114 may be formed on both side surfaces of the ceramic body 110 in the width direction, to which the ends of the internal electrodes 121 and 122 are exposed.
The thickness of the first side margin 113 and the second side margin 114 may be 18 μm or less. As the thickness of the first side margin 113 and the second side margin 114 is smaller, the overlapping area of the internal electrodes formed in the ceramic body may be further increased.
The thickness of the first side margin 113 and the second side margin 114 is not particularly limited as long as it has a thickness that may prevent the short of the internal electrode exposed to the side of the laminate 111. For example, the thicknesses of the first side margin 113 and the second side margin 114 may be 2 μm or more.
If the thickness of each of the first and second side margins is less than 2 μm, the mechanical strength against external impact may be lowered. If the thickness of each of the first and second side margins is more than 18 μm, the overlapping area of the internal electrodes may be relatively reduced, and thus, it may be difficult to secure the high capacity of the multilayer ceramic capacitor.
To significantly increase the capacity of the multilayer ceramic capacitor, a method of thinning the dielectric layer, a method of high lamination of the thinned dielectric layers, a method of improving the coverage of the internal electrode, and the like have been considered.
In addition, a method of improving the overlap area of the internal electrodes forming the capacitance has been considered.
To increase the overlapping area of the internal electrodes, the margin area in which the internal electrodes are not formed should be significantly reduced.
In detail, as the multilayer ceramic capacitor becomes smaller, the margin area should be significantly reduced to increase the overlapping area of the internal electrodes.
According to this embodiment, the internal electrode is formed entirely in the width direction of the dielectric layer, and the thickness of the side margin is set to 18 μm or less, so that the overlapping area of the internal electrodes is relatively wide.
In general, the more the dielectric layers are highly laminated, the thinner the thickness of the dielectric layer and the internal electrode. Therefore, a phenomenon in which the internal electrode is shorted may occur more frequently. In addition, when the internal electrode is formed only on a portion of the dielectric layer, a step difference may occur due to the internal electrode, thereby increasing accelerated lifespan of the insulation resistance.
However, according to this embodiment, even when the internal electrode and the dielectric layer of the thin film are formed, since the internal electrode is formed entirely in the width direction of the dielectric layer, the overlapping area of the internal electrodes may be increased to increase the capacity of the multilayer ceramic capacitor.
In addition, a multilayer ceramic capacitor may have excellent capacitance characteristics and excellent reliability by reducing the step difference caused by the internal electrodes, to reduce accelerated lifespan of the insulation resistance.
On the other hand, in manufacturing a multilayer ceramic capacitor, in the related art, the dielectric composition of the ceramic body is used without differentiating the dielectric composition for forming the side margins from the dielectric composition of the ceramic body.
Thus, in this case, the physical packing density of the dielectric in the side margin is relatively low, thereby causing a problem in which the densification of the side margin is reduced, and due to the mismatching phenomenon of the sintering drive between the internal electrode and the dielectric of the side margin during the sintering process, there arises a problem in which the interface gap between the electrode end portion and the margin junction surface, inevitably generated, may not be filled.
In addition, the ceramic dielectric sheet serving as the side margin is attached to the green chip cut without the margin portion by physical compression, and then, the sintered body having a rigid body is formed through high temperature heat treatment. Thus, in a case in which the adhesive force between the electrode exposed surface and the sheet for forming margins in operation before sintering is insufficient, poor appearance due to side margin removal and serious defects leading to interfacial cracks may occur.
In addition, voids are generated between the electrode end and the margin interface when the volume change occurs inside the chip due to shrinkage of the internal electrode during high temperature heat treatment, acting as a starting point of crack generation or as a moisture penetration path, thereby causing a decrease in moisture resistance reliability.
Therefore, the dielectric of the margin region should have an excellent sintering driving force, so that the same sintered-body density as that of the ceramic body may be ensured, even with a low physical filling density, thereby significantly reducing the decrease in the strength of the multilayer ceramic capacitor.
In addition, the dielectric used in the margin region should be able to more actively move the material at a high temperature to fill the interface void.
In addition, the interface bonding force should be improved by forming an oxide layer on the end joining surface by reaction with the internal electrode.
According to an embodiment of the present disclosure, the dielectric composition included in the first and second side margins 113 and 114 and the dielectric composition included in the ceramic body 110 are different from each other.
The first and second side margins 113 and 114 include a barium titanate base material powder and a subcomponent, and the subcomponent includes terbium (Tb) as a first subcomponent including a lanthanide rare earth element. The content ratio of the terbium (Tb) to the content of the first subcomponent (RE) excluding the terbium (Tb) satisfies 0.110≤Tb/RE≤2.333. In one example, the content ratio of the present disclosure may refer to a mole ratio.
The first and second side margins 113 and 114 include a barium titanate base material powder and a subcomponent, and the subcomponent includes terbium (Tb) as a first subcomponent including a lanthanide rare earth element, and the above problem may be solved by adjusting the content ratio of terbium (Tb) to the content of the first subcomponent (RE) except for the terbium (Tb) to satisfy 0.110≤Tb/RE≤2.333.
In detail, according to an embodiment, a decrease in the interfacial adhesion between the internal electrode and the margin portion may be prevented, and the generation of voids between the internal electrode and the margin portion may be prevented, thereby improving reliability.
In addition, uniform oxide layer and insulating layer may be secured on the end of the internal electrode, to reduce short defects, and the density of the margin portion may be improved, and the mechanical strength of the multilayer ceramic capacitor and the high temperature/moisture reliability may be improved.
If the content ratio (Tb/RE) of the terbium (Tb) to the content of the first subcomponent (RE) excluding the terbium (Tb) is less than 0.110, the content of terbium (Tb) is relatively small and thus, voids generated between the internal electrode and the margin portion may not be effectively filled, degrading reliability.
If the content ratio (Tb/RE) of the terbium (Tb) to the content of the first subcomponent (RE) excluding the terbium (Tb) exceeds 2.333, the content of terbium (Tb) is excessive. Thus, there is a side effect accompanied by a decrease in dielectric layer insulation resistance due to an increase in leakage current due to the electron emission phenomenon by the reaction formula.
According to an embodiment, the content of the terbium (Tb) included in the first and second side margins 113 and 114 may satisfy 0.15 mol≤Tb≤1.35 mol with respect to 100 mol of the base material powder included in the first and second side margins 113 and 114.
Since the content of the terbium (Tb) included in the first and second side margins 113 and 114 satisfies 0.15 mol≤Tb≤1.35 mol with respect to 100 mol of the base metal powder included in the first and second side margins 113 and 114, a decrease in the interface adhesion between the internal electrode and the margin portion may be prevented and the reliability may be improved by preventing the generation of voids between the internal electrode and the margin.
In addition, the uniform oxide layer and insulating layer may be secured on the end of the internal electrode, to reduce short defects, to improve the density of the margin portion, and to improve the mechanical strength of the multilayer ceramic capacitor and improve the high temperature/moisture reliability.
If the content of terbium (Tb) is less than 0.15 mol compared to 100 mol of the base metal powder, the content of terbium (Tb) may be relatively small so that the gap between the internal electrode and the margin may not be effectively filled and reliability may be deteriorated.
If the content of terbium (Tb) exceeds 1.35 mol relative to 100 mol of the base metal powder, the content of terbium (Tb) is excessive, and due to an increase in leakage current due to electron emission generated by a defect chemical reaction equation, there is a side effect accompanied by a decrease in dielectric layer insulation resistance.
According to an embodiment of the present disclosure, the subcomponent includes magnesium (Mg) and barium (Ba), and the content ratio of magnesium (Mg) to content of the barium (Ba) may satisfy 0.125≤Mg/Ba≤0.500.
The subcomponent includes magnesium (Mg) and barium (Ba), by adjusting the content ratio of the magnesium (Mg) to the content of the barium (Ba) to satisfy 0.125≤Mg/Ba≤0.500, the interfacial adhesion between the internal electrode and the margin may be prevented from decreasing, and the reliability may be improved by preventing the formation of voids between the internal electrode and the margin.
In addition, the uniform oxide layer and insulating layer may be secured on the end of the internal electrode, to reduce short defects, to improve the density of the margin portion, and to improve the mechanical strength of the multilayer ceramic capacitor and improve the high temperature/moisture reliability.
If the content ratio (Mg/Ba) of the magnesium (Mg) to the content of the barium (Ba) is less than 0.125, problems such as deterioration of the density of margins, generation of interfacial voids, and uneven thicknesses of dielectric and internal electrode ends occur, and reliability may be degraded.
If the content ratio (Mg/Ba) of the magnesium (Mg) to the content of the barium (Ba) exceeds 0.500, the dielectric properties may decrease.
The content of magnesium (Mg) may satisfy 0.25 mol≤Mg≤1.0 mol compared to 100 mol of the base material powder.
By adjusting the content of magnesium (Mg) to satisfy 0.25 mol≤Mg≤1.0 mol compared to 100 mol of the base material powder, the degradation of the interfacial adhesion between the internal electrode and the margin portion may be prevented, the generation of voids between the internal electrode and the margin portion may be prevented, thereby improving the reliability.
In addition, it is possible to secure uniform oxide layer and insulating layer on the end of the internal electrode, to reduce short defects, to improve the density of the margin portion, and to improve the mechanical strength of the multilayer ceramic capacitor and improve the high temperature/moisture reliability.
If the content of magnesium (Mg) is less than 0.25 mol compared to 100 mol of the base metal powder, problems such as deterioration of margin density, generation of interfacial voids, and nonuniform thicknesses of the dielectric and internal electrode ends may occur, thereby reducing the reliability.
If the content of the magnesium (Mg) exceeds 1.0 mol compared to 100 mol of the base metal powder, dielectric properties may decrease.
As described above, the internal electrode is exposed in the width direction of the body, thereby significantly increasing the internal electrode area in the width direction through a margin-free design. In this case, in the case of manufacturing a multilayer ceramic capacitor by a method of separately attaching a margin portion to the electrode exposed surface of the chip in the width direction in the operation before firing after the fabrication of the chip, the upper and lower electrodes may be connected by the sliding phenomenon of the internal electrode exposed surface during the cutting process of the internal electrode exposed surface, which may cause a short circuit and a decrease in withstand voltage.
In addition, physical/chemical phenomena in which an interface is opened may occur due to a spontaneous reaction to lower surface energy due to a reduction in specific surface area during sintering at an interface at the time of performing heterojunction a metal and a ceramic.
Therefore, to solve both of these problems, it is necessary to select an element capable of forming a uniform oxide layer without forming a secondary phase, while having high affinity with nickel (Ni) used as an internal electrode and thus being easily able to be solid dissolved.
According to an embodiment of the present disclosure, with the same structure as NiO composed of a NaCl structure in which the cation and anion ratio is 1:1, and simultaneously, by controlling the absolute content ratio of Mg oxide having a high oxygen affinity, the bonding force with the side margin ceramic by generation of the oxide layer may be increased in addition to the even formation of an insulating layer on the nickel (Ni) electrode end.
In this case, in a case in which the content ratio of Mg exceeds an optimum composition ratio, the sinterability may be lowered and to be lowered due to the excessive Mg addition or the withstand voltage may decrease due to the generation of the secondary phase. Thus, the selection of the content ratio may be significantly important.
In addition, to further improve the withstand voltage of the multilayer ceramic capacitor including moisture resistance and to suppress crack generation, the densities of side margins should be secured, and the voids of electrode ends should be effectively filled. To this end, improving sintering driving force and inducing active mass transport at high temperatures are required.
The content of the barium (Ba) may satisfy 0.5 mol≤Ba≤3.0 mol with respect to 100 mol of the base material powder.
Detailed description of the content of the barium (Ba) will be described later.
According to an embodiment of the present disclosure, the subcomponent may include a second subcomponent which is an oxide or carbonate containing the Ba, and a third subcomponent with a content greater than 0.0 and less than 4.5 mol, including at least one of a carbonate or oxide having at least one of silicon (Si) or aluminum (Al), or glass compounds containing Si, with respect to 100 mol of the base material powder. The content ratio of the magnesium (Mg) relative to the total content of the barium (Ba) and silicon (Si) may satisfy 0.09≤Mg/(Ba+Si)≤0.19.
By adjusting the content ratio of the magnesium (Mg) to the total content of the barium (Ba) and silicon (Si) to satisfy 0.09≤Mg/(Ba+Si)≤0.19, the formation of voids between the internal electrode and the margin may be prevented, thereby improving reliability.
In addition, a uniform oxide layer and an insulating layer may be secured on the end of the internal electrode, to reduce short defects, to improve the density of the margin portion, and to improve the mechanical strength of the multilayer ceramic capacitor and improve the high temperature/moisture reliability.
If the content ratio (Mg/(Ba+Si)) of the magnesium (Mg) to the total content of the barium (Ba) and silicon (Si) is less than 0.09, problems such as deterioration of the density of margins and generation of interface voids occur, and reliability may decrease.
If the content ratio (Mg/(Ba+Si)) of magnesium (Mg) to the total content of barium (Ba) and silicon (Si) exceeds 0.19, the dielectric characteristics may be degraded by excessive diffusion of magnesium (Mg) into the active dielectric layer.
In detail, since barium (Ba) and silicon (Si) are important minor components that determine densification at low temperature by liquid phase sintering or the solubility limit in the BaTiO3 lattice such as terbium (Tb), magnesium (Mg) or the like, based on the eutectic line of binary phase diagrams in the two-element system, the interrelationship of the addition ratio thereof with terbium (Tb) and magnesium (Mg) may be important.
According to an embodiment of the present disclosure, the dielectric composition included in the first and second side margins 113 and 114 and the dielectric composition included in the ceramic body 110 are different from each other. The dielectric composition included in the first and second side margins 113 and 114 will be described.
a) Base Material Main Component
A dielectric ceramic composition included in the first and second side margins 113 and 114 according to an embodiment of the present disclosure may include a base material main component including barium (Ba) and titanium (Ti).
According to an embodiment, the base material main component is BaTiO3 or a main component represented by (Ba, Ca) (Ti, Ca) O3, (Ba, Ca) (Ti, Zr) O3, Ba (Ti, Zr) O3, or (Ba, Ca) (Ti, Sn) O3, in which Ca, Zr, Sn, or the like is partially dissolved. The base material main component may be included in powder form.
b) First Subcomponent
According to an embodiment, terbium (Tb) is included as a first subcomponent containing a lanthanide rare earth element, and in addition thereto, the first subcomponent having a content of greater than 0.0 and less than or equal to 4.0 mol, may be included, which is an oxide or carbonate including at least one of yttrium (Y), dysprosium (Dy), holmium (Ho), erbium (Er), gadolinium (Gd), cerium (Ce), neodymium (Nd), samarium (Sm), lanthanum (La), ytterbium (Yb) and praseodymium (Pr) with respect to 100 mol of the base metal powder.
The content of the first subcomponent may be provided based on the content of at least one of Tb, Y, Dy, Ho, Er, Gd, Ce, Nd, Sm, La, Yb and Pr included in the first subcomponent without distinguishing an addition form such as an oxide or a carbonate.
For example, the sum of the contents of at least one or more elements among Tb, Y, Dy, Ho, Er, Gd, Ce, Nd, Sm, La, Yb, and Pr included in the first subcomponent may be less than or equal to 4.0 mol, to 100 mol of the base material main component.
The first subcomponent prevents deterioration of reliability of the multilayer ceramic capacitor to which the dielectric ceramic composition is applied in one embodiment.
If the content of the first subcomponent exceeds 4.0 mol with respect to 100 mol of the base material main component, high temperature withstand voltage characteristics may be degraded due to pyrochlor (RE2Ti2O7) (where RE is at least one or more elements among Y, Dy, Ho, Er, Gd, Ce, Nd, Sm, La, Yb, and Pr) secondary phase.
c) Second Subcomponent
According to an embodiment of the present disclosure, the dielectric ceramic composition may include a second subcomponent including one or more selected from the group consisting of oxides and carbonates, a Mg element.
The second subcomponent may be included in an amount of 0.5 mol≤Mg≤3.0 mol with respect to 100 mol of the base material powder.
The content of the second subcomponent may be based on the content of Mg element included in the second subcomponent without distinguishing an addition form such as an oxide or a carbonate.
When the second subcomponent is included in an amount of 0.5 mol≤Mg≤3.0 mol with respect to 100 mol of the base material powder, high temperature withstand voltage characteristics may be improved.
d) Third Subcomponent
According to an embodiment, the dielectric ceramic composition may include a third subcomponent including at least one of an oxide or carbonate including at least one of Si, Ba and Al, or a glass compound including Si.
The third subcomponent may be included in an amount of more than 0.0 and less than 4.5 mol with respect to 100 mol of the base material powder.
The content of the third subcomponent may be based on the content of Si, Ba or Al elements included in the third subcomponent without distinguishing an addition form such as glass, oxide, or carbonate.
If the content of the third subcomponent is included in the amount of 4.5 mol or more with respect to 100 mol of the base metal powder, there may be problems such as lowering of sintering property and density, secondary phase generation, and the like.
A multilayer ceramic capacitor according to another embodiment includes a ceramic body including a first surface and a second surface opposing each other, and a third surface and a fourth surface connecting the first and second surfaces to each other, a plurality of internal electrodes disposed inside the ceramic body, exposed to the first and second surfaces, and having an end exposed to the third or fourth surface, and a first side margin and a second side margin disposed on end portions of the internal electrodes exposed to the first and second surfaces, respectively. The first and second side margins include a barium titanate base material powder and a subcomponent, and the subcomponent includes Terbium (Tb) as one subcomponent including a lanthanide rare earth element. In the first and second side margins, the content ratio of the terbium (Tb) to the content of the first subcomponent (RE) excluding the terbium (Tb) satisfies 0.110≤Tb/RE≤2.333. A dielectric composition included in the first and second side margins and a dielectric composition included in the ceramic body are different from each other. The content of the terbium (Tb) included in the first and second side margins is greater than the content of terbium (Tb) in the ceramic body. For example, a content ratio of the terbium (Tb) included in the first and second side margins to a content of the base material powder included in the first and second side margins, may be greater than a content ratio of terbium (Tb) included in the ceramic body to a content of a base material powder such as a barium titanate-based base powder included in the ceramic body.
According to another embodiment, the dielectric composition included in the first and second side margins 113 and 114 and the dielectric composition included in the ceramic body 110 are different from each other. The first and second side margins 113 and 114 include a barium titanate base material powder and a subcomponent, and the subcomponent includes terbium (Tb) as a first subcomponent including a lanthanide rare earth element, and the content ratio of the terbium (Tb) to the content of the first subcomponent (RE) except for the terbium (Tb) satisfies 0.110≤Tb/RE≤2.333, and the content ratio of the terbium (Tb) included in the first and second side margins 113 and 114 is more than the content ratio of terbium (Tb) contained in the ceramic body 110.
In the multilayer ceramic capacitor according to another embodiment, the dielectric composition included in the first and second side margins 113 and 114 and the dielectric composition included in the ceramic body 110 are different from each other. The content ratio of the terbium (Tb) included in the first and second side margins 113 and 114 is adjusted to be higher than the content ratio of terbium (Tb) included in the ceramic body 110, thereby to provide an effect according to an embodiment of the present disclosure.
In detail, according to another embodiment, the interfacial adhesion between the internal electrode and the margin portion may be prevented from being lowered, and the formation of voids between the internal electrode and the margin portion may be prevented, thereby improving reliability.
In addition, uniform oxide layer and insulating layer may be formed on the end of the internal electrode, to reduce short defects, to improve the density of the margin portion, and to improve the mechanical strength of the multilayer ceramic capacitor and improve the high temperature/moisture reliability.
Hereinafter, a method of manufacturing a multilayer ceramic capacitor according to another embodiment will be described.
FIGS. 5A to 5F are cross-sectional views and perspective views schematically illustrating a method of manufacturing a multilayer ceramic capacitor according to another embodiment.
As illustrated in FIG. 5A, a plurality of stripe-type first internal electrode patterns 221a are formed on a ceramic green sheet 212a at a predetermined interval d4. The plurality of stripe-type first internal electrode patterns 221a may be formed in parallel to each other.
The predetermined interval d4 is a distance for the internal electrodes to be insulated from the external electrode, having different polarities, and may be understood as a distance of d2×2 illustrated in FIG. 4.
The ceramic green sheet 212a may be formed of a ceramic paste including ceramic powder, an organic solvent, and an organic binder.
The ceramic powder is a material having a high dielectric constant, and although not particularly limited, as the ceramic powder, a barium titanate (BaTiO3)-based material, a lead composite perovskite-based material, a strontium titanate (SrTiO3)-based material, or the like may be used, and in detail, barium titanate (BaTiO3) powder may be used. When the ceramic green sheet 212a is fired, the ceramic green sheet 212a becomes the dielectric layer 112 constituting the ceramic body.
The stripe-type first internal electrode pattern 221a may be formed by an internal electrode paste containing a conductive metal. The conductive metal is not particularly limited, but may be nickel (Ni), copper (Cu), palladium (Pd), or alloys thereof.
The method of forming the stripe-type first internal electrode pattern 221a on the ceramic green sheet 212a is not particularly limited, but may be formed by, for example, a printing method such as a screen printing method or a gravure printing method.
Although not illustrated, a plurality of stripe-type second internal electrode patterns 222a (shown in FIG. 5B) may be formed on the other ceramic green sheet 212a at a predetermined interval.
Hereinafter, the ceramic green sheet on which the first internal electrode pattern 221a is formed may be referred to as a first ceramic green sheet, and the ceramic green sheet on which the second internal electrode pattern 222a is formed may be referred to as a second ceramic green sheet.
Next, as illustrated in FIG. 5B, the first and second ceramic green sheets may be alternately stacked so that the stripe-type first internal electrode patterns 221a and the stripe-type second internal electrode patterns 222a are alternately stacked.
Subsequently, the stripe first internal electrode pattern 221a may form the first internal electrode 121, and the stripe second internal electrode pattern 222a may form the second internal electrode 122.
FIG. 5C is a cross-sectional view illustrating a ceramic green sheet laminate 210 in which the first and second ceramic green sheets are stacked according to an embodiment, and FIG. 5D is a perspective view of the ceramic green sheet laminate 210 in which the first and second ceramic green sheets are stacked.
Referring to FIGS. 5C and 5D, a first ceramic green sheet on which a plurality of parallel stripe-type first internal electrode patterns 221a are printed, and a second ceramic green sheet on which a plurality of parallel stripe-type second internal electrode patterns 222a are printed are alternately stacked.
In more detail, the green sheets may be stacked in such a manner that the center of the stripe-shaped first internal electrode pattern 221a printed on the first ceramic green sheet and the interval d4 between the stripe-type second internal electrode patterns 222a printed on the second ceramic green sheet overlap each other.
Next, as illustrated in FIG. 5D, the ceramic green sheet laminate 210 may be cut to transverse the plurality of stripe-type first internal electrode patterns 221a and the stripe-type second internal electrode patterns 222a. For example, the ceramic green sheet laminate 210 may be cut into bar laminates 220 along line C1-C1.
In more detail, the stripe-type first internal electrode pattern 221a and the stripe-type second internal electrode pattern 222a may be cut in the length direction and divided into a plurality of internal electrodes having a predetermined width. At this time, the stacked ceramic green sheets are also cut together with the internal electrode patterns. Accordingly, the dielectric layer may be formed to have the same width as that of the internal electrode.
Ends of the first and second internal electrodes may be exposed to the cut surface of the bar laminate 220. The cut surfaces of the bar laminate may be referred to as first and second sides of the bar laminate, respectively.
The ceramic green sheet laminate may be fired and may then be cut into the bar laminates. In addition, firing may be performed after the ceramic green sheet is cut into the bar laminates. Although not particularly limited, the firing may be performed in an N2—H2 atmosphere of 1100° C. to 1300° C.
Next, as illustrated in FIG. 5E, a first side margin 213a and a second side margin 214a may be formed on the first and second side surfaces of the bar laminate 220, respectively. The second side margin 214a is not clearly illustrated, but is outlined in dotted line.
The first and second side margins 213a and 214a may be provided by forming a ceramic slurry including ceramic powder on the bar laminate 220.
The ceramic slurry may include a ceramic powder, an organic binder, and an organic solvent, and the amount of the ceramic slurry may be adjusted such that the first and second side margins 213a and 214a have a required thickness.
The first and second side margins 213a and 214a may be formed by applying a ceramic slurry to the first and second side surfaces of the bar laminate 220. The method of applying the ceramic slurry is not particularly limited, and may be applied by spraying or using a roller, for example.
In addition, the bar laminate may be dipped in the ceramic slurry to form the first and second side margins 213a and 214a on the first and second side surfaces of the bar laminate.
As described above, the thicknesses of the first and second side margins may be 18 μm or less.
Next, as illustrated in FIGS. 5E and 5F, the bar laminate 220 having the first and second side margins 113a and 114a formed thereon may be cut into individual chips with respectively required sizes, along a C2-C2 cutting line. FIG. 5C may be referred to determine the position of the C2-C2 cutting line.
As the bar laminate 220 is cut into chip size, a ceramic body having a laminated body 111 and the first and second side margins 113 and 114 formed on both sides of the laminated body may be formed.
As the bar laminate 220 is cut along the C2-C2 cutting line, a center portion of the overlapped first and second internal electrodes, and the predetermined interval d4 between the second internal electrodes, may be cut by the same cutting line. From another point of view, a central portion of the second internal electrode, and a predetermined interval between the first internal electrodes, may be cut by the same cutting line.
Accordingly, one ends of the first internal electrode and the second internal electrode may be alternately exposed to the cutting surface along the C2-C2 cutting line. The surface to which the first internal electrode is exposed may be understood to be the third surface 3 of the laminate illustrated in FIG. 4, and the surface to which the second internal electrode is exposed may be understood to be the fourth surface 4 of the laminate illustrated in FIG. 4.
As the bar laminate 220 is cut along the C2-C2 cutting line, the predetermined interval d4 between the sprite-type first internal electrode patterns 221a is cut in half, such that one end of the first internal electrode 121 is spaced apart from the fourth surface by a predetermined interval d2. In addition, one end of the second internal electrode 122 is allowed to be spaced apart from the third surface by a predetermined interval d2.
Thereafter, an external electrode may be formed on each of the third and fourth surfaces to be connected to one ends of the first and second internal electrodes.
As in this embodiment, when the first and second side margins are formed on the bar laminate 220 and cut into chip sizes, the side margins may be formed on a plurality of laminated bodies 111 through one process.
In addition, although not illustrated, a plurality of laminates may be formed by cutting the bar laminate into chip sizes before forming the first side margin and the second side margin.
For example, the bar laminate may be cut, such that the central portion of the overlapping first internal electrode, and a predetermined interval between the second internal electrodes, are cut by the same cutting line. Accordingly, one ends of the first internal electrode and the second internal electrode may be alternately exposed to the cut surface.
Thereafter, the first side margin and the second side margin, made of the above described material, may be formed on the first and second surfaces of the laminated body. A method of forming the first and second side margins is as described above.
In addition, an external electrode may be formed on a third surface of the laminated body to which the first internal electrode is exposed and another external electrode may be formed on a fourth surface of the laminated body to which the second internal electrode is exposed.
According to another embodiment, the ends of the first and second internal electrodes are exposed through the first and second surfaces of the laminate. The plurality of stacked first and second internal electrodes may be simultaneously cut, and thus, the ends of the internal electrodes may be disposed on one straight line. Thereafter, first and second side margins are collectively formed on the first and second surfaces of the laminate. The ceramic body is formed by the laminate and the first and second side margins. For example, the first and second side margins form on the first and second side surfaces of the ceramic body, respectively.
Accordingly, according to this embodiment, the distance from the ends of the plurality of internal electrodes to the first and second surfaces of the ceramic body may be uniformly formed. In addition, the first and second side margins are formed by a ceramic paste, and may have a relatively thin thickness.
Hereinafter, an embodiment of the present disclosure will be described in more detail with reference to an experimental example. However, the scope of the present disclosure is not limited by the experimental example.
Experimental Example
As a base material main component, a BaTiO3 powder of 100 nm or less was used, and a subcomponent composition in this case is illustrated in Table 1 below.
In preparing a slurry, the base material main component and subcomponent powder were mixed with ethanol/toluene and a dispersant by using zirconia balls as mixing/dispersing media, and then, mechanical milling was performed, and then a binder mixing process for implementing dielectric sheet strength was added.
The prepared slurry was manufactured into a sheet having a thickness of 10 to 20 μm to form a side margin using an on-roll coater of the head discharge method.
In addition, the sheet was attached to an electrode exposed portion of the green chip in which the internal electrode is exposed in the width direction and there is no margin, and was cut to have a size of 5 cm×5 cm to form the side margin.
A multilayer ceramic capacitor green chip of 0603 size (width×length×height: 0.6 mm×0.3 mm×0.3 mm) was fabricated by attaching the sheet to both sides of the chip by applying a constant temperature and pressure under the condition of significantly reducing chip deformation.
The fabricated multilayer ceramic capacitor specimen was subjected to a plasticizing process under nitrogen atmosphere at 400° C. or lower, and then subjected to firing under the conditions of firing temperature of 1200° C. or lower and hydrogen concentration of 0.5% H2 or less. Then, electrical characteristics, insulation resistance, chip strength, the adhesion at the interface between the side margin and internal electrode and void filling therebetween, the degree of formation of insulation layer on the electrode end, the difference in the density of the side margins and the like were comprehensively confirmed.
Dielectric loss and the room temperature capacitance of the multilayer ceramic capacitor (MLCC) for each composition were measured at 1 kHz and AC 0.5 V, using an LCR meter, and 50 samples were taken to measure a breakdown voltage (BDV), which causes breakdown.
Side margin hardness of the multilayer ceramic capacitor (MLCC) was measured using a Vickers hardness tester under 5 kgf load and holding time of 5 sec. The microstructures such as a margin density and an insulation layer generation degree were compared for a fracture surface and a polishing surface of the chip.
Table 1 below is a dielectric composition table of Experimental Example (Comparative Examples and Embodiment Examples), and BaTiO3 is used as a base material main component. In this case, as the subcomponent, an additional element in the form of a basic donor and acceptor constituting the multilayer ceramic capacitor (MLCC), and elements serving as a sintering aid including Ba—Si—Al were used.
At this time, to compare the densities of the side margins, the formation of an oxide layer on an electrode end, the void filling, and the interfacial adhesion according to Embodiment Examples of the present invention and Comparative Examples, the additive element content ratios were variously changed for respective subcomponents.
Table 2 below summarizes the electrical characteristics and microstructure results of the 0603 size multilayer ceramic capacitor (MLCC) corresponding to the composition specified in Table 1 above.
TABLE 1
Mole number of additive per 100 mol of BatiO3 base material
First
Subcomponent
Second
Third
total Tb in
total RE in
Subcomponent
Subcomponent
Main Subcomponent Ratio
Sample
Tb4O7
RE2O3
MgCO3
BaCO3
SiO2
Tb/RE
Mg/Ba
Mg/(Ba + Si)
*1
0.00
1.50
0.50
2.0
3.3
—
0.250
0.094
2
0.15
1.35
0.50
2.0
3.3
0.111
0.250
0.094
3
0.30
1.20
0.50
2.0
3.3
0.250
0.250
0.094
4
0.45
1.05
0.50
2.0
3.3
0.429
0.250
0.094
5
0.60
0.90
0.50
2.0
3.3
0.667
0.250
0.094
6
0.75
0.75
0.50
2.0
3.3
1.000
0.250
0.094
7
0.90
0.60
0.50
2.0
3.3
1.500
0.250
0.094
8
1.05
0.45
0.50
2.0
3.3
2.333
0.250
0.094
*9
1.20
0.30
0.50
2.0
3.3
4.000
0.250
0.094
*10
1.35
0.15
0.50
2.0
3.3
9.000
0.250
0.094
*11
1.50
0.00
0.50
2.0
3.3
—
0.250
0.094
*12
0.45
1.05
0.0
2.0
3.3
0.429
0.000
0.000
*13
0.45
1.05
0.25
2.0
3.3
0.429
0.125
0.047
14
0.45
1.05
0.75
2.0
3.3
0.429
0.375
0.142
15
0.45
1.05
1.00
2.0
3.3
0.429
0.500
0.189
*16
0.45
1.05
0.75
0.5
3.3
0.429
1.500
0.197
*17
0.45
1.05
0.75
1.0
3.3
0.429
0.750
0.174
18
0.45
1.05
0.75
1.5
3.3
0.429
0.500
0.156
19
0.45
1.05
0.75
2.5
3.3
0.429
0.300
0.129
20
0.45
1.05
0.75
3.0
3.3
0.429
0.250
0.119
*21
0.45
1.05
0.75
2.5
1.5
0.429
0.300
0.191
*22
0.45
1.05
0.75
2.5
4.5
0.429
0.300
0.107
TABLE 2
Structural Characteristics
Electrical Characteristics
Depth of
High
Oxide Layer
Interfacial
Body
Smoothness
Dielectric and
temperature
Moisture
on Electrode
void filling
Density
Interfacial
Strength
of Electrode
thickness
Dielectric
withstand
resistance
Short
Sample
Ends
rate
of Margin
Adhesion
of Margin
End
uniformity
constant
voltage
reliability
Rate
*1
Δ
X
X
X
X
X
X
◯
X
X
X
2
Δ
◯
Δ
◯
Δ
Δ
Δ
◯
Δ
Δ
Δ
3
Δ
Δ
◯
Δ
◯
◯
◯
◯
◯
◯
◯
4
Δ
◯
⊚
◯
⊚
◯
◯
◯
◯
⊚
◯
5
Δ
◯
⊚
◯
⊚
◯
◯
◯
Δ
◯
◯
6
Δ
◯
◯
◯
◯
◯
◯
◯
Δ
Δ
◯
7
Δ
◯
◯
◯
◯
◯
◯
◯
Δ
Δ
Δ
8
Δ
◯
◯
◯
◯
◯
◯
◯
Δ
Δ
Δ
9
Δ
◯
◯
◯
◯
Δ
Δ
◯
X
X
X
*10
Δ
Δ
Δ
Δ
Δ
X
X
◯
X
X
X
*11
Δ
X
X
X
X
X
X
◯
X
X
X
*12
X
X
Δ
Δ
Δ
X
X
⊚
X
X
X
*13
X
Δ
Δ
Δ
Δ
X
X
⊚
◯
◯
Δ
14
⊚
⊚
⊚
⊚
⊚
◯
◯
◯
⊚
⊚
⊚
15
⊚
⊚
⊚
⊚
⊚
⊚
⊚
Δ
◯
◯
⊚
*16
⊚
Δ
Δ
Δ
Δ
X
X
Δ
X
X
X
*17
⊚
Δ
◯
Δ
Δ
Δ
Δ
Δ
Δ
X
Δ
18
⊚
◯
⊚
◯
©
◯
◯
◯
Δ
◯
◯
19
⊚
⊚
⊚
⊚
⊚
⊚
⊚
◯
⊚
⊚
⊚
20
⊚
◯
◯
◯
◯
◯
◯
◯
◯
◯
⊚
*21
⊚
Δ
Δ
Δ
Δ
X
X
Δ
X
X
X
*22
⊚
⊚
Δ
◯
Δ
Δ
Δ
Δ
Δ
Δ
X
⊚: Excellent,
◯: Good,
Δ: Normal,
X: Poor
As illustrated in Table 1 and Table 2, when the ratio of terbium (Tb) in the rare earth element increases to a certain level or more, the interface void filling effect may be obtained by improving the body density and body strength and improving the material transfer driving force of the body. The content ratio of the terbium (Tb) to the content of the first subcomponent (RE), excluding the terbium (Tb), may be up to 9.0.
However, in consideration of the high temperature and moisture resistance reliability of the multilayer ceramic capacitor, in case of terbium (Tb) having a strong donor type tendency, in the case in which the content ratio is excessively high, leakage current increases due to the electron emission phenomenon generated by a defect chemical reaction equation. Since a side effect accompanied by a decrease in dielectric layer insulation resistance occurs, the content ratio of the terbium (Tb) to the content of the first subcomponent (RE) excluding the terbium (Tb) may satisfy 0.110≤Tb/RE≤2.333, to simultaneously obtain the effects of densification of the body and the increase of insulation resistance of the dielectric layer.
In addition, the content ratio of the magnesium (Mg) to the content of the barium (Ba) may satisfy 0.125≤Mg/Ba≤0.500.
By adjusting the content ratio of the magnesium (Mg) to the content of the barium (Ba) to satisfy 0.125≤Mg/Ba≤0.500, the degradation of the interfacial adhesion between the internal electrode and the margin may be prevented, and the generation of voids between the internal electrode and the margin may be prevented, thereby improving the reliability.
In addition, a uniform oxide layer and insulating layer on the end of the internal electrode may be secured, to reduce short defects, to improve the density of the margin portion, and to improve the mechanical strength of the multilayer ceramic capacitor and improve the high temperature/moisture resistance reliability.
In the case of samples 12, 16 and 17, the content ratio of magnesium (Mg) to the content of barium (Ba) is outside the numerical range according to an embodiment of the present disclosure. In this case, the margin density decreases, the interfacial voids occur, and the thickness uniformity on the dielectric and internal electrode ends may be lowered. Further, a decrease in dielectric properties may occur.
On the other hand, the content ratio of magnesium (Mg) to the total content of barium (Ba) and silicon (Si) may satisfy 0.09≤Mg/(Ba+Si)≤0.19.
In an embodiment in which the content ratio of magnesium (Mg) to the total content of the barium (Ba) and silicon (Si) satisfies 0.09≤Mg/(Ba+Si)≤0.19, void generation between the internal electrode and the margin portion may be prevented, and thus, it can be seen that the reliability may be improved.
In addition, the uniform oxide layer and insulating layer on the end of the internal electrode may be secured, to reduce short defects, to improve the density of the margin portion, and to improve the mechanical strength of the multilayer ceramic capacitor. Therefore, it can be seen that the high temperature/moisture resistance reliability may be improved.
In the case of Sample 13 in which the content ratio (Mg/(Ba+Si)) of magnesium (Mg) to the total content of barium (Ba) and silicon (Si) is less than 0.09, there is a problem in which the margin density decreases, the interfacial voids are generated, and the thickness uniformity on the internal electrode end decreases, thereby causing a decrease in reliability.
In the case of Sample 21 in which the content ratio (Mg/(Ba+Si)) of magnesium (Mg) to the total content of barium (Ba) and silicon (Si) exceeds 0.19, excessive diffusion of magnesium (Mg) into the active dielectric layer degrades dielectric properties.
In the case of sample 22, the content of silicon (Si) is out of the numerical range according to an embodiment of the present disclosure, which may cause problems of degrading sintering properties and density, and short generation.
As set forth above, according to an embodiment, after fabricating the chip in such a manner that the internal electrode is exposed in the width direction of the body, a decrease in the interfacial adhesion between the internal electrodes and the margins, occurring during the multilayer ceramic capacitor manufacturing process in which the margins are separately attached to the electrode exposed surface of the chip in the width direction, in operation before firing, may be prevented.
In addition, in the multilayer ceramic capacitor manufactured by the above manufacturing process, the generation of voids between the internal electrode and the margin portion may be prevented, thereby improving the reliability.
In addition, uniform oxide layer and insulating layer may be secured on the end of the internal electrode, thereby reducing short defects.
In addition, the density of the margin portion may be improved, thereby improving the mechanical strength of the multilayer ceramic capacitor and improving the high temperature/moisture resistance.
The internal electrode is formed entirely in the width direction of the dielectric layer, and is exposed to the side of the body in the width direction, and then, the margins are attached separately, thereby significantly increasing the overlapping area between the internal electrodes to implement a high capacity multilayer ceramic capacitor, and reducing the occurrence of step difference.
While this disclosure includes specific examples, it will be apparent to one of ordinary skill in the art that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed to have a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or replaced or supplemented by other components or their equivalents. Therefore, the scope of the disclosure is defined not by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.
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16887167
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samsung electro-mechanics co., ltd.
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USA
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B2
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Utility Patent Grant (with pre-grant publication) issued on or after January 2, 2001.
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Open
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Apr 27th, 2022 09:11AM
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Apr 27th, 2022 09:11AM
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Samsung
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krx:005930
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Samsung
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Apr 26th, 2022 12:00AM
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Sep 16th, 2020 12:00AM
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https://www.uspto.gov?id=US11316250-20220426
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Chip antenna and antenna module including chip antenna
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A chip antenna is provided. The chip antenna includes a first dielectric layer; a second dielectric layer disposed on an upper surface of the first dielectric layer; a patch antenna pattern disposed in the second dielectric layer; first and second feed vias disposed to penetrate through at least one of the first and second dielectric layers, respectively and electrically connected to a corresponding feed point among different first and second feed points of the patch antenna pattern; and first and second filters disposed between the first and second dielectric layers, respectively and electrically connected to a corresponding feed via among the first and second feed vias.
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11316250
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1. A chip antenna, comprising:
a first dielectric layer;
a second dielectric layer disposed on an upper surface of the first dielectric layer;
a patch antenna pattern disposed in the second dielectric layer;
a first feed via and a second feed via respectively disposed to penetrate through at least one of the first dielectric layer and the second dielectric layer, and electrically connected to a corresponding feed point among a first feed point and a second feed point of the patch antenna pattern; and
a first filter and a second filter disposed between the first dielectric layer and the second dielectric layer, and electrically connected to a corresponding feed via among the first feed via and the second feed via.
2. The chip antenna of claim 1, further comprising a first ground layer disposed between the first filter and the second filter and the patch antenna pattern,
wherein the first ground layer is configured to have a first hole and a second hole in which the first feed via and the second feed vias are respectively located.
3. The chip antenna of claim 2, further comprising a second ground layer disposed on a lower surface of the first dielectric layer,
wherein the second ground layer is configured to have a third hole and a fourth hole in which the first feed via and the second feed via are respectively located.
4. The chip antenna of claim 1, further comprising a ground layer disposed to be spaced apart upwardly or downwardly of the first filter and the second filter; and
a first ground via and a second ground via electrically connected between the ground layer and a corresponding filter among the first filter and the second filter.
5. The chip antenna of claim 4, wherein each of the first filter and the second filter comprises a first ring pattern having a first port, and configured to surround a first area; and
a second ring pattern having a second port, and configured to surround a second area,
wherein one of the first port and the second port is connected to a corresponding feed via among the first feed via and the second feed via, and another of the first port and the second port is connected to a corresponding ground via among the first ground via and the second ground via.
6. The chip antenna of claim 1, wherein each of the first filter and the second filter comprises a first ring pattern having a first port and surrounding a first area; and
a second ring pattern having a second port and surrounding a second area, and
wherein at least one of the first port and the second port is connected to a corresponding feed via among the first feed via and the second feed via.
7. The chip antenna of claim 6, wherein the first ring pattern and the second ring pattern are disposed to be spaced apart from each other, and have an open shape in a direction facing each other.
8. The chip antenna of claim 6, wherein the first filter is disposed such that the first ring pattern and the second ring pattern protrude from the first port and the second port in a first direction, and
the second filter is disposed such that the first ring pattern and the second ring pattern protrude from the first port and the second port in a second direction, different from the first direction.
9. The chip antenna of claim 1, further comprising an adhesive layer configured to adhere between the first dielectric layer and the second dielectric layer.
10. The chip antenna of claim 9, wherein the adhesive layer is configured to have a cavity to surround the first filter and the second filter.
11. The chip antenna of claim 10, wherein the adhesive layer is configured to have a ventilator between the cavity and an outer surface of the adhesive layer.
12. The chip antenna of claim 9, wherein the first dielectric layer and the second dielectric layer are respectively comprised of a ceramic material, and
the adhesive layer comprises a polymer.
13. The chip antenna of claim 1, further comprising a soldering pattern disposed on a lower surface of the first dielectric layer and arranged along an outer periphery of the first dielectric layer.
14. An antenna module, comprising
a substrate, in which at least one wiring layer and at least one insulating layer are alternately stacked; and
a chip antenna disposed on a first surface of the substrate,
wherein the chip antenna comprises
a first dielectric layer, configured to have a higher dielectric constant than a dielectric constant of the at least one insulating layer;
a second dielectric layer, disposed on an upper surface of the first dielectric layer, and configured to have a higher dielectric constant than the dielectric constant of the at least one insulating layer;
a patch antenna pattern disposed in the second dielectric layer;
a feed via disposed to penetrate through at least one of the first dielectric layer and the second dielectric layer, and electrically connected between the patch antenna pattern and the at least one wiring layer; and
a filter, disposed between the first dielectric layer and the second dielectric layer and electrically connected to the feed via.
15. The antenna module of claim 14, wherein the filter comprises a first ring pattern having a first port and surrounding a first area; and
a second ring pattern having a second port and surrounding a second area, and
wherein at least one of the first port and the second port is electrically connected to the feed via.
16. The antenna module of claim 14, wherein the chip antenna further comprises a ground layer, disposed to be spaced apart upwardly or downwardly of the filter; and
a ground via electrically connected between the ground layer and the filter.
17. An electronic device, comprising:
a base substrate comprising:
a communication modem;
a baseband integrated circuit (IC), and
at least one antenna module;
the at least one antenna module comprising:
a substrate;
a chip antenna, disposed on an upper surface of the substrate; and
an integrated circuit, disposed on a lower surface of the substrate;
wherein the chip antenna comprises:
a first dielectric layer, disposed adjacent to an upper surface of the substrate;
a filter, disposed on an upper surface of the first dielectric layer;
a second dielectric layer disposed above the filter, and
a feed via, configured to penetrate the first dielectric layer and the second dielectric layer, and further configured to electrically connect the chip antenna and the integrated circuit,
wherein the substrate comprises one or more alternately stacked wiring layers, and one or more alternately stacked insulating layers, and
wherein the first dielectric layer and the second dielectric layer are configured to have a higher dielectric constant than a dielectric constant of the insulating layers.
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17
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CROSS-REFERENCE TO RELATED APPLICATION(S)
This application claims the benefit under 35 USC § 119(a) of priority to Korean Patent Application No. 10-2020-0068918, filed on Jun. 8, 2020, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.
BACKGROUND
1. Field
The following description relates to a chip antenna and an antenna module including the chip antenna.
2. Description of Related Art
Mobile communications data traffic has been increasing rapidly over recent years. Technology has been actively developed to support such rapid data transfer or data traffic in real time in a wireless network. In an example, applications such as applications related to the contents of Internet of Things (IoT)-based data, augmented reality (AR), Virtual Reality (VR), live VR/AR combined with SNS, autonomous driving, Sync View (real-time image transmission from the user's point view using an ultra-small camera), and the like, may utilize communications, (for example, 5G communications, millimeter wave (mmWave) communications, and the like), that support the transmission and reception of large amounts of data.
An RF signal in a high frequency band (for example, 24 GHz, 28 GHz, 36 GHz, 39 GHz, 60 GHz, and the like) may be easily absorbed in a process of transmission, and may result in data loss. Accordingly, the quality of communications may be dramatically reduced. Thus, an antenna that is configured to communicate in a high frequency band may be implemented by an approach that is different from the typical antenna technology. Technological aspects such as additional power amplifiers that ensure antenna gain, the integration of an antenna and an RFIC, and effective isotropic radiated power (EIRP) may be necessary to reduce data loss.
SUMMARY
This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In a general aspect, a chip antenna includes a first dielectric layer; a second dielectric layer disposed on an upper surface of the first dielectric layer; a patch antenna pattern disposed in the second dielectric layer; a first feed via and a second feed via respectively disposed to penetrate through at least one of the first dielectric layer and the second dielectric layer, and electrically connected to a corresponding feed point among a first feed point and a second feed point of the patch antenna pattern; and a first filter and a second filter disposed between the first dielectric layer and the second dielectric layer, and electrically connected to a corresponding feed via among the first feed via and the second feed via.
The chip antenna may include a first ground layer disposed between the first filter and the second filter and the patch antenna pattern, wherein the first ground layer is configured to have a first hole and a second hole in which the first feed via and the second feed vias are respectively located.
The chip antenna may include a second ground layer disposed on a lower surface of the first dielectric layer, wherein the second ground layer is configured to have a third hole and a fourth hole in which the first feed via and the second feed via are respectively located.
The chip antenna may include a ground layer disposed to be spaced apart upwardly or downwardly of the first filter and the second filter; and a first ground via and a second ground via electrically connected between the ground layer and a corresponding filter among the first filter and the second filter.
Each of the first filter and the second filter may include a first ring pattern having a first port, and configured to surround a first area; and a second ring pattern having a second port, and configured to surround a second area, wherein one of the first port and the second port is connected to a corresponding feed via among the first feed via and the second feed via, and another of the first port and the second port is connected to a corresponding ground via among the first ground via and the second ground via.
Each of the first filter and the second filter may include a first ring pattern having a first port and surrounding a first area; and a second ring pattern having a second port and surrounding a second area, and wherein at least one of the first port and the second port is connected to a corresponding feed via among the first feed via and the second feed via.
The first ring pattern and the second ring pattern may be disposed to be spaced apart from each other, and have an open shape in a direction facing each other.
The first filter may be disposed such that the first ring pattern and the second ring pattern protrude from the first port and the second port in a first direction, and the second filter may be disposed such that the first ring pattern and the second ring pattern protrude from the first port and the second port in a second direction, different from the first direction.
The chip antenna may include an adhesive layer configured to adhere between the first dielectric layer and the second dielectric layer.
The adhesive layer may be configured to have a cavity to surround the first filter and the second filter.
The adhesive layer may be configured to have a ventilator between the cavity and an outer surface of the adhesive layer.
The first dielectric layer and the second dielectric layer may be respectively comprised of a ceramic material, and the adhesive layer may include a polymer.
The chip antenna may include a soldering pattern disposed on a lower surface of the first dielectric layer and arranged along an outer periphery of the first dielectric layer.
In a general aspect, an antenna module includes a substrate, in which at least one wiring layer and at least one insulating layer are alternately stacked; and a chip antenna disposed on a first surface of the substrate, wherein the chip antenna comprises a first dielectric layer, configured to have a higher dielectric constant than a dielectric constant of the at least one insulating layer; a second dielectric layer, disposed on an upper surface of the first dielectric layer, and configured to have a higher dielectric constant than the dielectric constant of the at least one insulating layer; a patch antenna pattern disposed in the second dielectric layer; a feed via disposed to penetrate through at least one of the first dielectric layer and the second dielectric layer, and electrically connected between the patch antenna pattern and the at least one wiring layer; and a filter, disposed between the first dielectric layer and the second dielectric layer and electrically connected to the feed via.
The filter may include a first ring pattern having a first port and surrounding a first area; and a second ring pattern having a second port and surrounding a second area, and wherein at least one of the first port and the second port is electrically connected to the feed via.
The chip antenna further comprises a ground layer, disposed to be spaced apart upwardly or downwardly of the filter; and a ground via electrically connected between the ground layer and the filter.
In a general aspect, an electronic device includes a base substrate comprising: a communication modem; a baseband integrated circuit (IC), and at least one antenna module; the at least one antenna module includes a substrate; a chip antenna, disposed on an upper surface of the substrate; an integrated circuit, disposed on a lower surface of the substrate; wherein the chip antenna includes a first dielectric layer, disposed adjacent to an upper surface of the substrate; a filter, disposed on an upper surface of the first dielectric layer; a second dielectric layer disposed above the filter, and a feed via, configured to penetrate the first dielectric layer and the second dielectric layer, and further configured to electrically connect the chip antenna and the integrated circuit.
The substrate may include one or more alternately stacked wiring layers, and one or more alternately stacked insulating layers.
The first dielectric layer and the second dielectric layer may have a higher dielectric constant than a dielectric constant of the insulating layers.
Other features and aspects will be apparent from the following detailed description, the drawings, and the claims.
BRIEF DESCRIPTION OF DRAWINGS
FIGS. 1A and 1B are perspective views illustrating an example structure of a chip antenna, in accordance with one or more embodiments.
FIGS. 2A and 2B are plan views illustrating layers in which filters are disposed in an example chip antenna, in accordance with one or more embodiments.
FIGS. 3A to 3E are perspective views illustrating a structure in which a portion in which a first filter is not disposed is cut in an example chip antenna, in accordance with one or more embodiments.
FIG. 4 is a side view illustrating an example chip antenna and an example antenna module including the same, in accordance with one or more embodiments.
FIGS. 5A and 5B are side views illustrating a substrate providing a mounting space of an example chip antenna, in accordance with one or more embodiments.
FIG. 6 is a plan view illustrating an arrangement in an example electronic device of a substrate on which an example chip antenna is arranged, in accordance with one or more embodiments.
Throughout the drawings and the detailed description, unless otherwise described or provided, the same drawing reference numerals will be understood to refer to the same elements, features, and structures. The drawings may not be to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience.
DETAILED DESCRIPTION
The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent after an understanding of the disclosure of this application. For example, the sequences of operations described herein are merely examples, and are not limited to those set forth herein, but may be changed as will be apparent after an understanding of the disclosure of this application, with the exception of operations necessarily occurring in a certain order. Also, descriptions of features that are known in the art may be omitted for increased clarity and conciseness.
The terminology used herein is for describing various examples only, and is not to be used to limit the disclosure. The articles “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises,” “includes,” and “has” specify the presence of stated features, numbers, operations, members, elements, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, members, elements, and/or combinations thereof.
Throughout the specification, when an element, such as a layer, region, or substrate, is described as being “on,” “connected to,” or “coupled to” another element, it may be directly “on,” “connected to,” or “coupled to” the other element, or there may be one or more other elements intervening therebetween. In contrast, when an element is described as being “directly on,” “directly connected to,” or “directly coupled to” another element, there can be no other elements intervening therebetween.
As used herein, the term “and/or” includes any one and any combination of any two or more of the associated listed items.
Although terms such as “first,” “second,” and “third” may be used herein to describe various members, components, regions, layers, or sections, these members, components, regions, layers, or sections are not to be limited by these terms. Rather, these terms are only used to distinguish one member, component, region, layer, or section from another member, component, region, layer, or section. Thus, a first member, component, region, layer, or section referred to in examples described herein may also be referred to as a second member, component, region, layer, or section without departing from the teachings of the examples.
Unless otherwise defined, all terms, including technical and scientific terms, used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains after an understanding of the disclosure of this application. Terms, such as those defined in commonly used dictionaries, are to be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the disclosure of the present application, and are not to be interpreted in an idealized or overly formal sense unless expressly so defined herein.
FIGS. 1A and 1B are perspective views illustrating a structure of an example chip antenna, in accordance with one or more embodiments.
Referring to FIGS. 1A and 1B, example chip antennas 100a and 100b, in accordance with one or more embodiments, may include a first dielectric layer 131, a second dielectric layer 132, a patch antenna pattern 110, and a feed via 120, and a filter 170a.
In an example, the first and second dielectric layers 131 and 132 may each have a dielectric medium having a higher dielectric constant than air. In an example, the first and second dielectric layers 131 and 132 may be formed of ceramic, and may thus have a higher dielectric constant than that of an insulating layer (e.g., prepreg) of the substrate. The ceramic formation of the first and second dielectric layers 131 and 132 is only an example, and other materials may be used.
The chip of the chip antenna 100a means that the chip antenna 100a is a component that can be separately manufactured and disposed on a substrate providing a dispositional space of the chip antenna 100a, and may be disposed on the structure. Accordingly, the first and second dielectric layers 131 and 132 may be formed of a material different from an insulating layer of the substrate 200 (FIG. 4), and may be implemented in a more diverse and freely selected manner than the insulating layer.
In an example, the first and second dielectric layers 131 and 132 may be formed of a ceramic-based material such as low-temperature co-fired ceramic (LTCC), or a material having a relatively high dielectric constant, such as a glass-based material, or a material such as teflon, and may further contain at least one of magnesium (Mg), silicon (Si), aluminum (Al), calcium (Ca), and titanium (Ti), such that it may be configured to have higher dielectric constant or stronger durability. In an example, the first and second dielectric layers 131 and 132 may include Mg2SiO4, MgAlO4, and CaTiO3.
The higher the dielectric constants of the first and second dielectric layers 131 and 132, the shorter the wavelength of a radio frequency (RF) signal transmitted or propagated around the first and second dielectric layers 131 and 132. The shorter the wavelength of the RF signal, the smaller the size of the first and second dielectric layers 131 and 132, and the smaller the size of the chip antenna 100a according to an embodiment of the present disclosure.
The smaller the size of the chip antenna 100a, the greater the number of chip antennas 100a that can be arranged in a unit volume. The greater the number of chip antennas 100a that can be arranged in a unit volume, the higher the total gain and/or maximum output power compared to the unit volume of the plurality of chip antennas 100a.
Therefore, the higher the dielectric constants of the first and second dielectric layers 131 and 132, the greater the efficiency of size-to-size performance of the chip antenna 100a may be effectively improved.
In an example, the first and second dielectric layers 131 and 132 may be disposed to be spaced apart from each other. Accordingly, the space between the first and second dielectric layers 131 and 132 may be comprised of air or a medium lower than the dielectric constant of the first and second dielectric layers 131 and 132.
Accordingly, a space between the first and second dielectric layers 131 and 132 and a boundary surface between the first dielectric layers 131 may achieve a first dielectric boundary condition, and a space between the first and second dielectric layers 131 and 132 and a boundary surface between the second dielectric layers 132 may achieve a second dielectric boundary condition.
Since the first and second dielectric boundary conditions may refract a propagation direction of an RF signal, the first and second dielectric boundary conditions may more effectively concentrate a radiation pattern of the patch antenna pattern 110 in a vertical direction (for example, a z direction), and may improve a gain of the chip antenna 100a.
In a non-limiting example, the patch antenna pattern 110 may be disposed on the second dielectric layer 132. A relatively wide upper surface of the patch antenna pattern 110 may concentrate a radiation pattern in a vertical direction (for example, a z direction), so that a RF signal can be remotely transmitted and/or received in the vertical direction, and a RF signal having a frequency within a bandwidth based on a resonance frequency of the patch antenna pattern 110 may be remotely transmitted and/or received.
In an example, the shape of the patch antenna pattern 110 may be polygonal or circular, and the patch antenna pattern 110 may be configured to be a plurality of patch antenna patterns disposed to overlap each other in the vertical direction (e.g., the z direction). The sizes of the plurality of patch antenna patterns 110 may be different from each other, and may be electromagnetically coupled to each other. When the number of patch antenna patterns 110 increases, the number of the second dielectric layers 132 may also increase. In an example, the plurality of patch antenna patterns 110 and the plurality of second dielectric layers 132 may be alternately stacked vertically. In an example, one of the plurality of patch antenna patterns 110 may be a radiator, and the other thereof may have a relatively small size to feed the radiator in a non-contact manner.
In an example, the patch antenna pattern 110 may be formed as a conductive paste, and may be applied on the second dielectric layer 132 and dried.
The feed via 120 may be disposed to penetrate through the first dielectric layer 131, and may serve as a feed path of the patch antenna pattern 110. That is, the feed via 120 may provide a path through which a surface current flowing in the patch antenna pattern 110 flows when the patch antenna pattern 110a remotely transmits and/or receives an RF signal.
In an example, the feed via 120 may have a structure extending vertically in the first dielectric layer 131, and may be formed through a process in which a conductive material (e.g., copper, nickel, tin, silver, gold, palladium, and the like) is filled in a through hole by a laser.
The feed via 120 may include a first feed via 121 and a second feed via 122. The first and second feed vias 121 and 122 may be disposed to penetrate through at least one of the first and second dielectric layers 131 and 132, respectively, and may be electrically connected to different first and second feed points FP1 and FP2 of the patch antenna pattern 110.
The first feed via 121 may provide a transmission/reception path of a first RF signal, and the second feed via 122 may provide a transmission/reception path of a second RF signal. The first RF signal may carry first communication information, and the second RF signal may carry second communication information.
Since the chip antenna 100a according to an embodiment can remotely transmit and receive the first and second RF signals through the first and second feed vias 121 and 122 simultaneously, it may have a higher data transmission rate.
The first feed via 121 may be connected by being biased in a first direction (e.g., an x direction) from a center of the patch antenna pattern 110, and the second feed via 122 may be connected by being biased in a second direction (e.g., a y direction) different from the first direction from the center of the patch antenna pattern 110.
Accordingly, a first surface current corresponding to the first RF signal transmitted through the first feed via 121, may flow in the first direction from the patch antenna pattern 110, and a second surface current corresponding to the second RF signal transmitted through the second feed via 122 may flow from the patch antenna pattern 110 in a second direction.
Assuming that the first and second directions are perpendicular to each other, a first electric field and a first magnetic field of the first RF signal that radiates based on the first surface current, may be formed in the first direction and the second direction, respectively, and a second electric field and a second magnetic field of the second RF signal that radiates based on the second surface current may be formed in the second direction and the first direction, respectively.
Accordingly, the first and second RF signals can be radiated without substantial interference and cancellation with respect to each other, and the chip antenna 100a according to an example may improve comprehensive gains of the first and second RF signals.
A filter 170a may be disposed between the first and second dielectric layers 131 and 132, and can be electrically connected to the feed via 120.
The filter 170a may have a resonance frequency close to a fundamental frequency (e.g., 28 GHz, 39 GHz) of the RF signal remotely transmitted and received from the patch antenna pattern 110, and may have a band to which the fundamental frequency of the RF signal belongs. The resonance frequency may be determined according to a combination in inductance and capacitance of the filter 170a.
For example, the filter 170a may pass a frequency component in a band and block the remaining frequency components when it has a band pass characteristic, and block a frequency component in a band and block the remaining frequency components when it has a band block characteristic.
When the filter 170a is connected in series with the transmission/reception path of the RF signal, the filter 170a may reflect frequency components to be blocked to be filtered.
When the filter 170a is connected to the transmission/reception path of the RF signal by a shunt connection, the filter 170a may transmit the frequency component passed by the filter 170a to the first and/or second ground layers 181 and 182 to be filtered.
Since the filter 170a may filter harmonics and/or noise included in the RF signal, interference between the chip antenna 100a and an adjacent antenna according to an example may be reduced, and interference between a communication channel of the chip antenna 100a (e.g., a 5G communications channel, a millimeter wave communications channel) and a communications channel of adjacent channels (e.g., LTE) may be reduced, and it can help to comply with an electromagnetic compatibility (EMC) standard of the electronic device in which the chip antenna 100a is disposed.
Since the harmonics and/or noise included in the RF signal may be introduced into the RF signal according to remote transmission and reception in the patch antenna pattern 110, the filtering efficiency of the filter 170a may be more efficient closer to the patch antenna pattern 110.
Additionally, since energy of the RF signal may be lost according to the flow between the filter 170a and the patch antenna pattern 110, energy efficiency according to the filtering of the filter 170a may be higher as an electrical length between the filter 170a and the patch antenna pattern 110 is shorter.
Since the chip antenna 100a according to an example may include the patch antenna pattern 110 and the filter 170a together, it may be configured such that the patch antenna pattern 110 and the filter 170a are adjacent to each other, and the filtering efficiency and energy efficiency of the filter 170a may be improved.
Additionally, since the filter 170a may be disposed between the first and second dielectric layers 131 and 132, the filter 170a may have a further reduced size based on the relatively high dielectric constant of the first and second dielectric layers 131 and 132 (e.g., a high dielectric constant of the ceramic material). Therefore, the filter 170a may efficiently have a structure in which a plurality of filters are disposed in one layer.
The filter 170a may include a first filter 171a and a second filter 172a. The respective first and second filters 171a and 172a may be disposed between the first and second dielectric layers 131 and 132, respectively, and may be electrically connected to a corresponding feed via among the first and second feed vias 121 and 122.
Some components of the first RF signal transmitted and received through the first feed via 121 and some components of the second RF signal transmitted and received through the second feed via 122 may act as harmonics and/or noise with respect to each other.
The first and second filters 171a and 172a may filter harmonics and/or noise according to an influence of the first and second RF signals with respect to each other.
Accordingly, the chip antenna 100a according to an example may not only reduce interference between the chip antenna 100a and adjacent antennas, but may also further reduce interference of the first and second RF signals to each other, to improve comprehensive gains of the first and second RF signals.
In an example, the first and second filters 171a and 172a may be disposed on the same level as each other, or may be disposed on different levels.
Referring to FIG. 1A, the chip antenna 100a according to an embodiment of the present disclosure may further include at least one of a first ground layer 181, a second ground layer 182, and a ground via 183.
The first ground layer 181 may be disposed between the first and second filters 171a and 172a and the patch antenna 110.
Accordingly, electromagnetic interference between the first and second filters 171a and 172a and the patch antenna 110 with respect to each other can be reduced, and filtering efficiency of the first and second filters 171a and 172a and a gain of the patch antenna 110 can be improved.
The first ground layer 181 may have first and second holes TH21 and TH22 in which the first and second feed vias 121 and 122 are located, respectively, and may be spaced apart from the first and second feed vias 121 and 122.
The second ground layer 182 may be disposed on the lower surface of the first dielectric layer 131.
Accordingly, electromagnetic interference between the first and second filters 171a and 172a and a substrate with respect to each other can be reduced, so that the filtering efficiency of the first and second filters 171a and 172a can be improved.
The second ground layer 182 may have third and fourth holes TH11 and TH12 in which the respective first and second feed vias 121 and 122 are located, and may be spaced apart from the first and second feed vias 121 and 122.
The ground via 183 may electrically connect the first and/or second ground layers 181 and 182 and the first and second filters 171a and 172a.
Accordingly, the first and second filters 171a and 172a may be connected to the first and second feed vias 121 and 122 by a shunt connection, and may transmit harmonics and/or noise components mixed in the first and second RF signals flowing through the first and second feed vias 121 and 122 with respect to the first and second ground layers 181 and 182.
Referring to FIG. 1B, a chip antenna 100b according to an example may further include at least one of an adhesive layer 140a and a soldering pattern 160.
The adhesive layer 140a may be adhered to the first and second dielectric layers 131 and 132 between the first and second dielectric layers 131 and 132. Accordingly, a phenomenon in which one of the first and second dielectric layers 131 and 132 deviates may be suppressed, and a distance between the first and second dielectric layers 131 and 132 may be stably maintained.
The adhesive layer 140a may have a dielectric constant higher than a dielectric constant of air, and lower than a dielectric constant of the first and second dielectric layers 131 and 132. That is, when a dielectric constant of at least a portion of the space between the first and second dielectric layers 131 and 132 is lower than a dielectric constant of the adhesive layer 140a, a bandwidth and a gain, compared to the size of the chip antenna 100b, may be further improved.
Therefore, the adhesive layer 140a may have a cavity to surround the first and second filters 171a and 172a, and the cavity may provide a dielectric medium, lower than a dielectric medium of the adhesive layer 140a (e.g., air), such that it is possible to further improve a bandwidth and a gain compared to the size of the chip antenna 100b.
Since the dimensions or shape of the cavity may affect the resonant frequency or performance of the chip antenna 100b, the chip antenna 100a may have a structure that reduces a phenomenon in which the dimension or shape of the cavity deviates from the designed dimension or shape in the manufacturing process, so that performance may be more stably obtained.
Additionally, since the adhesive layer 140a may have a shorter width as the cavity is provided, the adhesive layer 140a may have a relatively floating structural stability compared to when the cavity 141 is not provided. Therefore, the chip antenna 100b may have a structure that reduces factors that physically affect the adhesive layer 140a in a manufacturing process thereof, so that performance can be more stably obtained.
Therefore, the adhesive layer 140a may have a ventilator 142a between the cavity and an outer surface of the adhesive layer 140a.
For example, in the manufacturing process of the chip antenna 100b, when the first and second dielectric layers 131 and 132 are bonded by the adhesive layer 140a, the chip antenna 100b may receive stress causing a change in volume of the cavity, and the cavity may distort the size or shape of the cavity or cause cracks in the first and second dielectric layers 131 and 132.
The ventilator 142a may reduce the influence of the stress on the chip antenna 100b by providing an air movement path of the cavity when the chip antenna 100b receives the stress that causes a change in volume of the cavity.
Accordingly, the chip antenna 100b according to an embodiment of the present disclosure may reduce a phenomenon in which dimensions or a shape of a cavity deviates from designed dimensions or a shape in a manufacturing process, or a factor physically affecting the adhesive layer 140a. Since it can be reduced, it is possible to more stably obtain improved performance (bandwidth and gain compared to size) based on the cavity.
In an example, the adhesive layer 140a may include a polymer having higher adhesion than the dielectric materials of the first and second dielectric layers 131 and 132. Since the adhesive polymer may have fluid characteristics compared to the ceramic structure, it may have an instability factor in the dimensions or shape of the cavity, the chip antenna 100b according to an example may include a ventilator 142a, so that it is possible to stably have a cavity of the adhesive layer 140a including an adhesive polymer having viscosity.
In an example, one outer surface of the adhesive layer 140a, one side surface of the first dielectric layer 131, and one side surface of the second dielectric layer 132 may form one plane. That is, the chip antenna 100b according to an example may have a form in which a side surface of the structure is cut in a structure in which the adhesive layer 140a is attached to the first and second dielectric layers 131 and 132.
In an example, the adhesive layer 140a may be disposed between the first ground layer 181 and the filter 170a illustrated in FIG. 1A. Accordingly, the adhesive layer 140a may stably support a spacing distance between the first ground layer 181 and the filter 170a.
In an example, a soldering pattern 160 may be disposed on a lower surface of the first dielectric layer 131, and may be arranged along an outer periphery of the first dielectric layer 131.
Accordingly, the chip antenna 100b may be more stably mounted on a substrate providing a dispositional space of the chip antenna 100a. The soldering pattern 160 may be electrically connected to the ground plane of the substrate.
In an example, the soldering pattern 160 may be configured to be advantageous for coupling to a tin-based solder having a relatively low melting point, and may be configured to facilitate coupling to the solder by including a tin plating layer and/or a nickel plating layer, and may have a structure in which a plurality of cylinders are arranged, but is not limited thereto.
Referring to FIG. 1B, the first feed via 121 may include a first-1 feed via 121-1 and a first-2 feed via 121-2, and the second feed via 122 may include a second-1 feed via 122-1 and a second-2 feed via 122-2.
The first-1 feed via 121-1 and the first-2 feed via 121-2 may be disposed so as not to overlap in the vertical direction (e.g., a z-direction), and the second-1 feed via 122-1 and the second-2 feed via 122-2 may be disposed so as not to overlap in the vertical direction (e.g., the z direction).
The first filter 171a may be electrically connected between the first-1 feed via 121-1 and the first-2 feed via 121-2, and the second filter 172a may be electrically connected between the second-1 feed via 122-1 and the second-2 feed via 122-2.
That is, the first filter 171a may be connected in series with the first feed via 121, and the second filter 172a may be connected in series with the second feed via 122.
FIGS. 2A and 2B are plan views illustrating a layer on which a filter is disposed in the chip antenna according to an example.
Referring to FIG. 2A, the first filter 171a may include first ring patterns 171-1a and 171-2a and second ring patterns 171-5a and 171-6a, and the second filter 172a may include first ring patterns 172-1a and 172-2a and second ring patterns 172-5a and 172-6a.
In an example, the first ring patterns 171-1a, 171-2a, 172-1a, and 172-2a may have a shape having a first port P11 and surrounding first areas 171-4a and 172-4a.
In an example, the second ring patterns 171-5a, 171-6a, 172-5a, and 172-6a may have a shape having a second port P22 and surrounding second areas 171-8a and 172-8a.
Accordingly, the respective first and second filters 171a and 172a may have high inductance, compared to a size thereof, such that the first and second filters 171a and 172a may have a more efficiently designed resonance frequency.
One of the first and second ports P11 and P12 may be connected to a feed via, and the other thereof may be connected to a ground via. Accordingly, the first and second filters 171a and 172a may be connected to the feed via respectively, by a shunt connection.
The first ring patterns 171-1a, 171-2a, 172-1a, and 172-2a and the second ring patterns 171-5a, 171-6a, 172-5a, and 172-6a may be disposed to be spaced apart from each other, and may have an open shape in a direction facing each other. In an example, the first filter 171a may have first openings 171-3a and 171-7a, and the second filter 172a may have second openings 172-3a and 172-7a.
Accordingly, the first and second filters 171a and 172a may have a high capacitance, respectively, compared to a size thereof, such that the first and second filters 171a and 172a may have a more efficiently designed resonance frequency.
The first filter 171a may be disposed such that the first ring patterns 171-1a and 171-2a and the second ring patterns 171-5a and 171-6a protrude in a first direction (for example:−x direction), and the second filter 172a may be disposed such that the second ring patterns 172-5a and 172-6a protrude in a second direction (for example: +x direction).
Referring again to FIG. 2A, the first filter 171b may include a first extension pattern 171-1b, a second extension pattern 171-2b, and third ring patterns 171-3b, 171-4b, 171-5b, and 171-6b, and may be included in a chip antenna according to an example. The second filter included in the chip antenna may have the same shape as the first filter 171b.
Accordingly, the first filter 171b may have a larger inductance and/or capacitance compared to a size thereof, such that the first filter 171b may have a more efficiently designed resonance frequency.
Referring to FIG. 2B, the first extension pattern 171-1b may have a first width W11, the second extension pattern 171-2b may have a second width W12, and the third ring pattern 171-3b, 171-4b, 171-5b, and 171-6b may have third widths Wa, Wb, Wc, and Wd.
The first extension pattern 171-1b may be spaced apart from the third ring patterns 171-3b, 171-4b, 171-5b, and 171-6b by a first distance G11, and the second extension pattern 171-2b may be spaced apart from the third ring patterns 171-3b, 171-4b, 171-5b, and 171-6b by a second distance G12.
The third ring patterns 171-3b, 171-4b, 171-5b, and 171-6b may have a length in a direction (Lx) in a X direction, may be longer than a first length (Dd), and may form an internal space of a second length (De).
FIGS. 3A to 3E are perspective views illustrating a structure in which a portion in which a first filter is not disposed, is cut in a chip antenna, in accordance with one or more embodiments.
Referring to FIG. 3A, the chip antenna 100a-1 may include a first dielectric layer 131-1 having a dispositional space 131-2 that includes the first filter 171a.
Referring to FIG. 3B, the chip antenna 100a-2 may include a first dielectric layer 131 having a length Ly in an x-direction and a length Lx in a y-direction.
Referring to FIGS. 3C and 3D, the chip antennas 100a-3 and 100a-4 may include a first filter 171a electrically connected between the feed via 120 and the ground via 183, and may include first and second side surface ground members 184 and 185 disposed on side surfaces of the first and second dielectric layers 131 and 132 in an x direction.
Referring to FIG. 3E, a chip antenna 100a-5 may include a patch antenna pattern 110 disposed on an upper surface of the second dielectric layer 132.
FIG. 4 is a side view illustrating a chip antenna and an antenna module including the same, in accordance with one or more embodiments.
Referring to FIG. 4, a chip antenna 100b, in accordance with one or more embodiments, may be disposed on one surface (e.g., an upper surface) of the substrate 200, and may be mounted on the substrate 200 through a soldering pattern 160.
The substrate 200 may have a structure in which at least one of the wiring layers 201, 202, 203, and 204, are alternately stacked, and may have a structure in which at least one of the insulating layers 211, 212, and 213 are alternately stacked, and a structure, similar to the structure of the printed circuit board.
The wiring layer 202 may surround a wiring 222 included in the substrate 200, and the insulating layers 211, 212 and 213 may surround vias 221 and 223 included in the substrate 200. The vias 221 and 223 and the wiring 222 may electrically connect feed vias 120-1 and 120-2 of the chip antenna 100b and an integrated circuit (IC) 310.
The IC 310 may be mounted on the lower surface of the substrate 200 through an electrical connection structure 330.
First and second dielectric layers 131 and 132 of the chip antenna 100b may have a higher dielectric constant than a dielectric constant of at least one of the insulating layers 211, 212 and 213 of the substrate 200.
Accordingly, a filter 170a may have a more reduced size based on the high dielectric constants of the first and second dielectric layers 131 and 132, and may effectively have a structure in which a plurality of filters are disposed in one layer, and the total height of the chip antenna 100b may be reduced.
FIGS. 5A and 5B are side views illustrating a substrate providing a mounting space of a chip antenna according to an embodiment of the present disclosure.
Referring to FIG. 5A, a substrate 200, on which the chip antenna according to an example is mounted, may provide at least one dispositional space of an IC 310, an adhesive member 320, an electrical connection structure 330, an encapsulant 340, a passive component 350, and a core member 410.
The IC 310 may be disposed downwardly of the substrate 200, and the IC 310 may perform at least a portion of frequency conversion, amplification, filtering, phase control, and power generation for remotely transmitted and/or received RF signals from the chip antenna according to an example. The IC 310 may be electrically connected to a wiring of the substrate 200 to transmit or receive an RF signal, and may be electrically connected to a ground plane of the substrate 200 to receive a ground.
The adhesive member 320 may bond the IC 310 and the substrate 200 to each other.
The electrical connection structure 330 may electrically connect the IC 310 and the substrate 200. For example, the electrical connection structure 330 may have a structure such as, but not limited to, a solder ball, a pin, a land, a pad, and the like. The electrical connection structure 330 may have a melting point, that is lower than a melting point of a wiring and a ground plane of the substrate 200, and thus may allow the IC 310 and the substrate 200 to be electrically connected to each other through a predetermined process using the low melting point.
The encapsulant 340 may seal at least a portion of the IC 310, thereby improving heat dissipation performance and an impact protection performance of the IC 310. For example, the encapsulant 340 may be provided as a photoimagable encapsulant (PIE), an Ajinomoto build-up film (ABF), an epoxy molding compound (EMC), or the like.
The passive component 350 may be disposed on a lower surface of the substrate 200, and may be electrically connected to a wiring and/or a ground plane of the substrate 200 through the electrical connection structure 330. In an example, the passive component 350 may include at least one among, as non-limiting examples, a capacitor (for example: a multilayer ceramic capacitor (MLCC)), an inductor, and a chip resistor.
The core member 410 may be disposed below the substrate 200, and may be electrically connected to the substrate 200 to receive an intermediate frequency (IF) signal or a baseband signal from an external source to transmit the IF signal or the baseband signal to the IC 310, or to receive an IF signal or a baseband signal from the IC 310 to transmit the IF signal or the baseband signal to an external source. Here, a frequency (e.g., 24 GHz, 28 GHz, 36 GHz, 39 GHz, and 60 GHz) of an RF signal may be greater than a frequency of an IF signal (for example: 2 GHz, 5 GHz, 10 GHz, and the like).
In an example, the core member 410 may transmit an IF signal or a baseband signal to the IC 310, or receive the IF signal or the baseband signal from the IC 310 through a wiring that can be included in an IC ground plane of the substrate 200.
Referring to FIG. 5B, a substrate 200 on which the chip antenna according to an example is mounted may include at least a portion of a shielding member 360, a connector 420, and an end-fire chip antenna 430.
The shielding member 360 may be disposed below the substrate 200, and may be disposed to confine the IC 310 together with the substrate 200. In an example, the shielding member 360 may be disposed to cover (for example, conformal shield) the IC 310 and the passive component 350, or may be disposed to cover (for example, compartment shield) each of the IC and the passive component. In an example, the shielding member 360 may have a hexahedral shape of which one side thereof is open, and may have a hexahedral accommodation space through coupling with the substrate 200. The shielding member 360 may be formed of a material having high conductivity such as copper to have a short skin depth, and may be electrically connected to a ground plane of the substrate 200. Thus, the shielding member 360 may reduce electromagnetic noise that can be received by the IC 310 and the passive component 350.
The connector 420 may have a connection structure of a cable (for example, a coaxial cable, a flexible PCB), may be electrically connected to an IC ground plane of the substrate 200, and may perform a role similar to that of the core member 410 described above. That is, the connector 420 may receive an IF signal, a baseband signal, and/or power from a cable, or may provide the IF signal and/or the baseband signal to the cable.
The end-fire chip antenna 430 may transmit or receive an RF signal in support of the chip antenna module according to an example. In an example, the end-fire chip antenna 430 may include a dielectric block having a dielectric constant greater than that of an insulating layer, and may include a plurality of electrodes disposed on both sides of the dielectric block. One among the plurality of electrodes may be electrically connected to a wiring of the substrate 200, and the other thereof may be electrically connected to a ground plane of the substrate 200.
FIG. 6 is a plan view illustrating an arrangement in an electronic device of a substrate on which a chip antenna according to an example is arranged.
Referring to FIG. 6, a plurality of antenna modules 100a-1 and 100a-2 according to an example may be disposed adjacent to a plurality of different edges of the electronic device 700, respectively.
The electronic device 700 may be, as non-limiting examples, a smartphone, a personal digital assistant (PDA), a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game machine, a smartwatch, an automotive component, or the like, but is not limited thereto.
The electronic device 700 may include a base substrate 600, and the base substrate 600 may further include a communication modem 610 and a baseband IC 620.
The communication modem 610 may include at least one among a memory chip such as a volatile memory (for example, a dynamic random access memory (DRAM)), a non-volatile memory (for example, a read only memory (ROM)), a flash memory, or the like; an application processor chip such as a central processor (for example, a central processing unit (CPU)), a graphic processor (for example, a graphic processing unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like; and a logic chip such as an analog-to-digital converter (ADC), an application-specific integrated circuit (ASIC), or the like to perform digital signal processing.
The baseband IC 620 may generate a base signal by performing analog-to-digital conversion, amplification for an analog signal, filtering, and frequency conversion. The base signal, input and output from the baseband IC 620, may be transmitted to chip antenna assemblies 100a-1 and 100a-2 through a coaxial cable, and the coaxial cable may be electrically connected to an electrical connection structure of the chip antenna assemblies 100a-1 and 100a-2.
In an example, the frequency of the base signal may be in a baseband, and may be a frequency (e.g, several GHz) corresponding to an intermediate frequency (IF). The frequency of the RF signal may be higher than the IF, and may correspond to millimeter waves (mmWave).
The pattern, the via, the plane, the strip, the line, and the electrical connection structure, disclosed herein, may include a metal material (for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, or the like), and may be formed using a plating method such as chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, subtractive, additive, a semi-additive process (SAP), a modified semi-additive process (MSAP), or the like, but it is not limited thereto.
The RF signal, disclosed herein, may include protocols such as wireless fidelity (W-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, or the like), worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, or the like), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high speed packet access+(HSPA+), high speed downlink packet access+(HSDPA+), high speed uplink packet access+(HSUPA+), enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth®, 3G, 4G, and 5G protocols, and any other wireless and wired protocols, designated after the abovementioned protocols, but is not limited thereto.
As set forth above, according to an example, a chip antenna may reduce interference between a chip antenna and adjacent antennas by including a filter, and may reduce interference between a communication channel (e.g., 5G communication channel, millimeter wave communication channel) of a chip antenna 100a and a communication channel of adjacent antennas (e.g., Wi-Fi, LTE).
According to an example, a chip antenna may have an advantageous structure to be disposed close to each other, such that it is possible to improve a filtering efficiency and an energy efficiency of a filter, and it is possible to reduce the size of the filter.
According to an example, a chip antenna can effectively filter harmonics and/or noise caused by expanding the transmission/reception path while having a data transmission/reception rate by extending the number of transmission/reception paths of the radio frequency (RF) signal, can improve comprehensive gains of the plurality of transmission/reception paths.
While this disclosure includes specific examples, it will be apparent after an understanding of the disclosure of this application that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or replaced or supplemented by other components or their equivalents. Therefore, the scope of the disclosure is defined not by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.
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17022239
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samsung electro-mechanics co., ltd.
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USA
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B2
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Utility Patent Grant (with pre-grant publication) issued on or after January 2, 2001.
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Open
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Apr 27th, 2022 09:11AM
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Apr 27th, 2022 09:11AM
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Samsung
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krx:005930
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Samsung
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Apr 26th, 2022 12:00AM
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May 18th, 2020 12:00AM
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https://www.uspto.gov?id=US11315738-20220426
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Tantalum capacitor and manufacturing method thereof
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A tantalum capacitor includes: a tantalum body having a tantalum wire exposed from one surface of the tantalum body; a molded portion including first and second surfaces opposing in a thickness direction, third and fourth surfaces opposing in a width direction, and fifth and sixth surfaces opposing in a longitudinal direction, the molded portion surrounding the tantalum body; an anode lead frame including an anode connection member and an anode terminal, which are connected to the tantalum wire, exposed through the second surface of the molded portion; and a cathode lead frame spaced apart from the anode lead frame, and exposed through the second surface of the molded portion, wherein end portions of the tantalum wire, the anode connection member, and the anode terminal in the longitudinal direction are on a same plane.
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11315738
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1. A tantalum capacitor, comprising:
a tantalum body having a tantalum wire exposed from one surface of the tantalum body;
a molded portion including first and second surfaces opposing each other in a thickness direction, third and fourth surfaces opposing each other in a width direction, and fifth and sixth surfaces opposing each other in a longitudinal direction, the molded portion surrounding the tantalum body;
an anode lead frame including an anode connection member and an anode terminal, which are connected to the tantalum wire, exposed through the second surface of the molded portion; and
a cathode lead frame spaced apart from the anode lead frame, and exposed through the second surface of the molded portion,
wherein end portions of the tantalum wire, the anode connection member, and the anode terminal in the longitudinal direction are on a same plane,
wherein an insulating layer, which is different from the molded portion, is disposed between the tantalum body and the anode lead frame, and
wherein the insulating layer is exposed to the second surface of the molded portion and spaced apart from the cathode lead frame.
2. The tantalum capacitor of claim 1, wherein the end portions of the tantalum wire, the anode connection member, and the anode terminal in the longitudinal direction include a cut surface.
3. The tantalum capacitor of claim 1, wherein a length of the anode connection member in the longitudinal direction is 0.2 mm or less.
4. The tantalum capacitor of claim 1, wherein the anode connection member has a square columnar shape.
5. The tantalum capacitor of claim 1, wherein the anode connection member has a cylindrical shape.
6. The tantalum capacitor of claim 1, wherein the tantalum wire and the anode connection member include a welded joint.
7. The tantalum capacitor of claim 1, wherein the insulating layer is in contact with a bottom surface of the tantalum body facing the second surface of the molded portion, and in contact with the anode connection member and the anode terminal.
8. The tantalum capacitor of claim 7, wherein a maximum thickness of the insulating layer in the thickness direction is consistent with a shortest distance from the bottom surface of the tantalum body to the second surface of molded portion.
9. The tantalum capacitor of claim 1, wherein a conductive adhesive layer is disposed between the tantalum body and the cathode lead frame.
10. The tantalum capacitor of claim 1, wherein a ratio (v1/v2) is 43% or more, where ‘v1’ refers to a volume of the tantalum body and ‘v2’ refers to a volume of the molded portion.
11. The tantalum capacitor of claim 1, wherein a distance between the tantalum body and the fifth surface of the molded portion is 0.45 mm or less.
12. A manufacturing method of a tantalum capacitor, comprising operations of:
mounting a tantalum capacitor, which includes a tantalum body having a tantalum wire exposed from one surface thereof, on an anode lead frame, which includes an anode terminal and an anode connection member, and a cathode lead frame;
cutting the anode terminal, the anode connection member, and the tantalum wire; and
disposing an insulating layer between the tantalum body and the anode lead frame and forming a molded portion which is different from the insulating layer,
wherein the insulating layer is exposed to one surface of the molded portion and spaced apart from the cathode lead frame.
13. The manufacturing method of the tantalum capacitor of claim 12, further comprising an operation of forming the anode lead frame, which includes the anode terminal and the anode connection member, and the cathode lead frame before the operation of mounting a tantalum capacitor.
14. The manufacturing method of the tantalum capacitor of claim 12, further comprising an operation of bonding the anode connection member and the tantalum wire after the operation of mounting a tantalum capacitor.
15. A tantalum capacitor, comprising:
a tantalum body having a tantalum wire exposed from one surface of the tantalum body;
a molded portion including first and second surfaces opposing each other in a thickness direction, third and fourth surfaces opposing each other in a width direction, and fifth and sixth surfaces opposing each other in a longitudinal direction, the molded portion surrounding the tantalum body;
an anode lead frame including an anode connection member and an anode terminal, which are connected to the tantalum wire, exposed through the second surface of the molded portion; and
a cathode lead frame spaced apart from the anode lead frame, and exposed through the second surface of the molded portion,
wherein the tantalum wire, the anode connection member, and the anode terminal are exposed to an outside of the tantalum capacitor through the fifth surface of the tantalum body in the longitudinal direction, and
wherein an insulating layer, which is different from the molded portion, is disposed between the tantalum body and the anode lead frame, and
wherein the insulating layer is exposed to the second surface of the molded portion and spaced apart from the cathode lead frame.
16. The tantalum capacitor of claim 15, wherein end portions of the tantalum wire, the anode connection member, and the anode terminal in the longitudinal direction are on a same plane.
17. The tantalum capacitor of claim 15, wherein a conductive adhesive layer is disposed between the tantalum body and the cathode lead frame.
18. The tantalum capacitor of claim 15, wherein a ratio (v1/v2) is 43% or more, where ‘v1’ refers to a volume of the tantalum body and ‘v2’ refers to a volume of the molded portion.
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18
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CROSS-REFERENCE TO RELATED APPLICATION
The present application claims the benefit of priority to Korean Patent Application No. 10-2019-0165449, filed on Dec. 12, 2019 with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.
TECHNICAL FIELD
The present disclosure relates to a tantalum capacitor and a manufacturing method thereof.
BACKGROUND
A tantalum (Ta) material is a metal having mechanical or physical characteristics such as a high melting point, excellent ductility and excellent corrosion-resistance, and is widely used in various fields throughout industries such as the electrical, electronic, mechanical, chemical, aerospace, and defense industries. Since the tantalum material may form a stable anodic oxide film, tantalum has been widely used as a material in forming anodes for small capacitors. Recently, in accordance with the rapid development of information technology (IT) industries, such as electronics information and communications technology (ICT) and electronics technology, tantalum has been increasingly used on a year-on-year basis.
Conventional tantalum capacitors use a structure in which a terminal is extracted externally by using a structure using an internal lead frame or a structure using without an internal lead frame or frame, in order to connect the tantalum material and the electrode.
In this case, in the case of a structure using an internal lead frame, a space occupied by tantalum material in the molded portion may be reduced by a lead frame constituting an anode and a cathode, and since capacitance is proportional to a volume of the tantalum material, there may be a problem with a limitation of the capacitance. In the case of a structure in which a terminal is extracted externally without a frame, there has been a problem in that ESR of the capacitor increases because contact resistance by a plurality of contact materials increases as a number of contact materials exist.
In addition, in the case of a structure in which a terminal is extracted externally without a conventional frame, since an internal volume fraction of the tantalum material is reduced because a welding distance for welding an anode wire and an anode lead frame should be necessarily secured, there is a problem in which the capacitance decreases.
SUMMARY
An aspect of the present disclosure is to provide a tantalum capacitor capable of realizing high capacity.
Another aspect of the present disclosure is to provide a tantalum capacitor having excellent reliability by improving mechanical strength.
Another aspect of the present disclosure is to provide a tantalum capacitor by improving a breakdown voltage (BDV) by increasing a withstand voltage.
According to an aspect of the present disclosure, a tantalum capacitor includes: a tantalum body having a tantalum wire exposed from one surface; a molded portion including first and second surfaces opposing each other in a thickness direction, third and fourth surfaces opposing each other in a width direction, and fifth and sixth surfaces opposing each other in a longitudinal direction, the molded portion surrounding the tantalum body; an anode lead frame including an anode connection member and an anode terminal, which are connected to the tantalum wire, exposed through the second surface of the molded portion; and a cathode lead frame spaced apart from the anode lead frame, and exposed through the second surface of the molded portion. End portions of the tantalum wire, the anode connection member, and the anode terminal in the longitudinal direction may be on a same plane.
According to another embodiment of the present disclosure, a manufacturing method of a tantalum capacitor include operations of: mounting a tantalum capacitor including a tantalum body in which a tantalum wire is exposed from one surface on an anode lead frame including an anode terminal and an anode connection member and a cathode lead frame; and cutting the anode terminal, the anode connection member, and the tantalum wire.
According to still another embodiment of the present disclosure, a tantalum capacitor includes: a tantalum body having a tantalum wire exposed from one surface; a molded portion including first and second surfaces opposing each other in a thickness direction, third and fourth surfaces opposing each other in a width direction, and fifth and sixth surfaces opposing each other in a longitudinal direction, the molded portion surrounding the tantalum body; an anode lead frame including an anode connection member and an anode terminal, which are connected to the tantalum wire, exposed through the second surface of the molded portion; and a cathode lead frame spaced apart from the anode lead frame, and exposed through the second surface of the molded portion. The tantalum wire, the anode connection member, and the anode terminal are exposed to an outside of the tantalum capacitor through the fifth surface of the tantalum body in the longitudinal direction.
BRIEF DESCRIPTION OF DRAWINGS
The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
FIGS. 1 and 2 are perspective views illustrating a tantalum capacitor according to an exemplary embodiment of the present disclosure;
FIGS. 3 and 4 are side views of FIGS. 1 and 2;
FIG. 5 is a plan view of FIG. 1 of the present disclosure;
FIG. 6 is a side view of a tantalum capacitor according to another exemplary embodiment of the present disclosure;
FIGS. 7A to 7E are schematic views illustrating operations of manufacturing a tantalum capacitor according to an exemplary embodiment of the present disclosure; and
FIG. 8 is a graph showing differences between Examples and Comparative Examples of the present disclosure.
DETAILED DESCRIPTION
Hereinafter, embodiments of the present disclosure will be described as follows with reference to the attached drawings. It is not intended to limit the techniques described herein to specific embodiments, and it should be understood to include various modifications, equivalents, and/or alternatives to the embodiments of the present disclosure. In connection with the description of the drawings, similar reference numerals may be used for similar components.
In the drawings, for clarity of description, parts irrelevant to the description may be omitted, and thicknesses of elements may be magnified to clearly represent layers and regions. Components having the same functions within a scope of the same idea may be described using the same reference numerals.
In the present specification, expressions such as “having”, “may have”, “include” or “may include” may indicate a presence of corresponding features (e.g., components such as numerical values, functions, operations, components, or the like), and may not exclude a presence of additional features.
In the present specification, expressions such as “A or B”, “at least one of A or/and B” or “one or more of A or/and B”, and the like, may include all possible combinations of items listed together. For example, “A or B”, or “at least one of A or B” may refer to all cases including (1) at least one A (2) at least one B, or (3) both at least one A and at least one B.
In the drawings, an X direction may be defined as a first direction, an L direction or a longitudinal direction, a Y direction as a second direction, a W direction or a width direction, and a Z direction as a third direction, a T direction, or a thickness direction.
A value used to describe a parameter such as a 1-D dimension of an element including, but not limited to, “length,” “width,” “thickness,” diameter,” “distance,” “gap,” and/or “size,” a 2-D dimension of an element including, but not limited to, “area” and/or “size,” a 3-D dimension of an element including, but not limited to, “volume” and/or “size”, and a property of an element including, not limited to, “roughness,” “density,” “weight,” “weight ratio,” and/or “molar ratio” may be obtained by the method(s) and/or the tool(s) described in the present disclosure. The present disclosure, however, is not limited thereto. Other methods and/or tools appreciated by one of ordinary skill in the art, even if not described in the present disclosure, may also be used.
FIGS. 1 and 2 are schematic perspective views of a tantalum capacitor according to an exemplary embodiment of the present disclosure, and FIGS. 3 and 4 are side views of FIGS. 1 and 2.
Referring to FIGS. 1 to 4, a tantalum capacitor 100 includes: a tantalum body 110 having a tantalum wire 120 exposed through one end surface, a molded portion 150 including fifth and sixth surfaces S5 and S6 facing in a first direction, third and fourth surfaces S3 and S4 facing in a second direction, and first and second surfaces S1 and S2 facing in a third direction, the molded portion 150 being formed to surround the tantalum body 110; an anode lead frame 130 including an anode connection member 131 and an anode terminal 132, which are connected to the tantalum wire 120, exposed through the second surface S2 of the molded portion 150; and a cathode lead frame 140 spaced apart from the anode lead frame 130 and exposed through the second surface S2 of the molded portion 150.
In this case, an end portion of the tantalum wire 120, the anode connection member 131, and the anode terminal 132 in the first direction may be on the same plane. Referring to FIGS. 2 and 4, the tantalum wire 120 may have an end portion (A), the anode connection member 131 and the anode terminal 132 may have an end portion (B). The end portion (A) of the tantalum wire 120 and the end portion of the anode connection member 131 and the anode terminal 132 may be disposed toward the first direction (X direction) of the molded portion 150, respectively. That is, the end portion (A) of the tantalum wire 120 and the end portion (B) of the anode connection member 131 and the anode terminal 132 may face the fifth surface S5 of the molded portion 150. The end portions (A) and (B) in the first direction of the tantalum wire 120, the anode connection member 131, and the anode terminal 132 are on the same plane, which may include an error range, and the error range may be, for example, within a range of ±0.5 mm. The tantalum capacitor 100 according to the present disclosure may have a structure in which the end portion (A) of the tantalum wire 120 and the end portion (B) of the anode connection member 131 and the anode terminal 132 are disposed on the same plane, as described above, and the tantalum wire 120 can be disposed as close as possible to the fifth surface S5 of the molded portion 150, thereby increasing an effective volume of the tantalum body inside the molded portion 150. In other words, the tantalum wire 120, the anode connection member 131, and the anode terminal 132 may be exposed to an outside of the tantalum capacitor 100 through the fifth surface S5 of the tantalum body 110 in the first direction.
In one example, the end portion (A) of the tantalum wire 120 applied to the tantalum capacitor 100 of the present disclosure and the end portion (B) of the anode connection member 131 and the anode terminal 132 may be a cutting surface formed by cutting. An anode lead frame of a general tantalum capacitor is manufactured by cutting and pressing a conductive thin plate, or the like to form an electrode plate, and welding an anode connection member, or the like to an upper surface of the electrode plate. In this case, in order to perform a separate welding process, a space that is capable of welding is required. In addition, a precise process of accurately positioning the anode connection member at a specific position on the upper surface of the electrode plate may be required for welding, and short circuits may occur as a welding material, or the like, is applied, and particularly, as the tantalum capacitor is miniaturized, these problems as described above occur more frequently. Moreover, for the process of bonding the tantalum wire to the anode connection member, since the tantalum wire must satisfy the minimum required length, there was a physical limitation of increasing the volume of the tantalum body, which is a capacitance part.
The above-described problems can be solved by cutting the end portion (A) of the tantalum wire 120 and the end portion (B) of the anode connection member 131 and the anode terminal 132. When the tantalum wire 120, the anode connection member 131, and the anode terminal 132 are first bonded and then cut them to form a cutting surface, welding is not necessary through a fine position adjustment, as the manufacturing method as described later, and it is possible to provide a tantalum capacitor having a wire length shorter than a minimum required length of the wire but not causing problems such as short.
In an exemplary embodiment of the present disclosure, the anode lead frame 130 may be made of a conductive metal such as a nickel/iron alloy, and may include an anode connection member 131 and an anode terminal 132. The anode terminal 132 of the anode lead frame 130 may be exposed through the second surface S2 of the molded portion 150. The anode terminal 132 may be exposed through a lower surface of the molded portion 150 to serve as a terminal when mounted on a substrate. In this case, the anode terminal 132 may be disposed to be spaced apart from the tantalum body 110, and a space in which the anode terminal 132 and the tantalum body 110 are spaced apart may be filled with a resin component, or the like, constituting the molded portion 150 to be described later.
In an exemplary embodiment of the present disclosure, a length of the anode connection member 131 included in the anode lead frame 130 in the first direction may be 0.2 mm or less. The length of the anode connection member 131 in the first direction may be a length in the X direction, and referring to FIG. 4, it may mean a length of (y−x). The length of the anode connection member 131 in the first direction may be 0.2 mm or less, 0.19 mm or less, 0.18 mm or less, 0.17 mm or less, 0.16 mm or less, or 0.15 mm or less, a lower limit thereof is not particularly limited, and for example, it may be exceed 0 mm or exceed 0.01 mm. The length of the anode connection member 131 in the first direction of the present embodiment may be implemented by having a structure in which the end portion (A) of the tantalum wire 120 and the end portion (B) of the anode connection member 131 and the anode terminal 132 are disposed on the same plane, as described above.
In an exemplary embodiment of the present disclosure, the anode connection member 131 included in the anode lead frame 130 may have a square columnar shape. FIG. 5 is a cross-sectional view illustrating a tantalum capacitor according to an exemplary embodiment of the present disclosure. Referring to FIG. 5, the anode connection member 131 of the present embodiment may have a square columnar shape, but is not limited thereto. For example, in another example of the present disclosure, the anode connection member 131 included in the anode lead frame 130 may have a cylindrical shape.
In another exemplary embodiment of the present disclosure, the tantalum wire 120 and the anode connection member 131 may include a welded joint. Even if the tantalum wire 120 and the anode connection member 131 are attached by welding, the tantalum capacitor 100 according to the present disclosure may have a high mechanical strength compared to an adhesive layer, or the like, while having a high withstand voltage and breakdown voltage, by having a high body volume, and thus excellent electrical properties and mechanical reliability may be compatible. The welding may use a spot welding or a laser welding, but is not limited thereto.
In an exemplary embodiment of the present disclosure, a groove into which the tantalum wire 120 is fitted and coupled may be disposed at a portion where the anode connection member 131 is connected to the tantalum wire 120. The groove may be formed on a surface of the anode connection member 131 in the Z direction, and the tantalum wire may be fitted into and coupled to the groove. In this case, the tantalum wire and the anode connection member 131 may be U-shaped, semi-circular, V-shaped, or square, but are not limited thereto. The method for forming such a groove is not particularly limited, and may be formed, for example, by punching or cutting a portion of the anode connection member 131.
The anode lead frame 130 and the cathode lead frame 140 of the tantalum capacitor 100 according to the present disclosure may be made of a conductive metal such as a nickel/iron alloy. The anode lead frame 130 may include an anode lead connection member 131 and an anode terminal 132, and the anode lead frame 130 the anode terminal 132 may be manufactured separately and then attached by welding or the like, or they may be integrally formed.
The anode lead frame 130 and the cathode lead frame 140 of the tantalum capacitor 100 according to the present disclosure may include an anode connection portion and a cathode connection portion that are mounted on a substrate, respectively. The anode connection portion and the cathode electrode connection portion include one of a conductive material, such as chromium titanium an intermetallic compound (Cr (Ti)), copper (Cu), nickel (Ni), palladium (Pd), gold (Au), or a combination thereof, and may be formed by a sputter deposition method or a plating method, but is not limited thereto.
The tantalum body 110 of the tantalum capacitor 100 according to the present disclosure is formed by using a tantalum material, for example, may be manufactured by mixing and stirring a tantalum (Ta) powder and a binder at a certain ratio, and compressing the mixed powder into a generally cuboid form, and then sintered under high temperature and high vacuum.
In addition, the tantalum body 110 may have a tantalum wire 120 exposed in the X direction of the tantalum body 110. The tantalum wire 120 may be mounted by inserting it into a mixture of the tantalum powder and the binder so as to be eccentric from the center before compressing the powder mixed with the tantalum powder and the binder. That is, the tantalum body 110 may be manufactured by inserting a tantalum wire 120 into a tantalum powder mixed with a binder to form a tantalum element having a desired size, and then by sintering the tantalum element in a high-temperature and high-vacuum (10−5 torr or less) atmosphere for about 30 minutes.
In an exemplary embodiment of the present disclosure, an insulating layer 270 may be disposed between a tantalum body 210 and an anode lead frame 230 of a tantalum capacitor 200. FIG. 6 is a side view of the tantalum capacitor 200 according to another exemplary embodiment of the present disclosure. Referring to FIG. 6, an insulating layer 270 may be disposed in a space between the anode lead frame 230, including the anode connection member 231 and the anode terminal 232, and the tantalum body 210. The insulating layer 270 is not particularly limited as long as it has sufficient insulating properties. For example, a polymer resin, ceramic, or the like may be exemplified, but is not limited thereto. When an insulating layer 270 is disposed between the tantalum body 210 and the anode lead frame 230, in the manufacturing process of the tantalum capacitor 200 of the present disclosure, even if some parts deviate from a desired position, defects such as shorts, or the like, can be prevented.
In one exemplary embodiment of the present disclosure, the insulating layer 270 may be in contact with a bottom surface of the tantalum body 210 facing the second surface S2 of a molded portion 250, and in contact with the anode connection member 231 and the anode terminal 232 of the anode lead frame 230. In one exemplary embodiment, a maximum thickness of the insulating layer 270 in the T direction may be consistent with a shortest distance from the bottom surface of the tantalum body 210 to the second surface S2 of molded portion 250.
In the above-described embodiment, a distance between the tantalum body 210, on which the insulating layer 270 is disposed, and the anode lead frame in the X direction may be 0.10 mm or more.
Referring to FIG. 4, a distance (x) between the tantalum body 110 and the anode lead frame 130 may mean a shortest vertical distance between the tantalum body 110 and the anode connection member 131 in the X direction. The distance (x) between the tantalum body 110 and the anode lead frame 130 may be 0.10 mm or more, 0.11 mm or more, 0.12 mm or more, 0.13 mm or more, 0.14 mm or more, or 0.15 mm or more, and an upper limit thereof is particularly limited, but may be, for example, 2 mm or less. When the distance (x) between the tantalum body 110 and the anode lead frame 130 satisfies the above-described range, short occurrence can be effectively suppressed.
In another exemplary embodiment of the present disclosure, a conductive adhesive layer 260 (or 160 in FIGS. 3 and 4) may be disposed between the tantalum body 210 and the cathode lead frame 240 of the tantalum capacitor 200. The conductive adhesive layer 260 may be formed by applying and curing a predetermined amount of a conductive adhesive containing an epoxy-based thermosetting resin and a conductive metal powder such as silver (Ag), but the present disclosure is not limited thereto. When the conductive adhesive layer 260 is applied to the tantalum capacitor 200 of the present disclosure, fixing strength of the cathode lead frame 240 can be improved.
The tantalum capacitor 100 according to the present disclosure may be surrounded by a molded portion 150. The molded portion 150 may be formed by transfer molding a resin such as an epoxy molding compound (EMC) to surround the tantalum body 110. The molded portion 150 may serve to protect the tantalum wire 120 and the tantalum body 110 from the outside, and may serve to insulate the tantalum body 110 and the anode lead frame 130 from each other.
In one example of the present disclosure, a ratio (v1/v2) of a volume (v1) of the tantalum body 110 to a volume (v2) of the molded portion 150 may be 43% or more. The volume (v2) of the molded portion 150 is a sum of both the anode lead frame 130 and the cathode lead frame 140 of the tantalum capacitor 100 according to the present disclosure, and may be substantially the volume of the tantalum capacitor 100. The ratio (v1/v2) of the volume (v1) of the tantalum body 110 to the volume (v2) of the molded portion 150 substantially represents a relative volume of the tantalum body 100 forming the capacitive portion, which shows that an effective capacity of the tantalum capacitor increases as the ratio (v1/v2) increases. The ratio (v1/v2) of the volume (v1) of the tantalum body 110 to the volume (v2) of the molded portion 150 may be 43% or more, 44% or more, 45% or more, 46% or more, 47% or more, or 48% or more, and an upper limit thereof is not particularly limited, but for example, may be 60% or less. The ratio (v1/v2) of the volume (v1) of the tantalum body 110 to the volume (v2) of the molded portion 150 is due to the structure unique to the present disclosure, which may be achieved by forming the tantalum wire shorter than a minimum required length.
In one example, the tantalum capacitor according to the present disclosure may have a distance between the tantalum body and the fifth surface of the molded portion may be 0.45 mm or less. Referring to FIG. 4, a distance (y) between the tantalum body 110 and the fifth surface S5 of the molded portion 150 may mean a shortest distance between the tantalum body 100 and the fifth surface S5 of the molded portion 150. The distance (y) between the tantalum body 110 and the fifth surface S5 of the molded portion 150 may be 0.45 mm or less, 0.44 mm or less, 0.43 mm or less, 0.42 mm or less, 0.41 mm or less, or 0.40 mm or less, and a lower limit thereof is not particularly limited, but may be, for example, 0.1 mm or more. When the distance (y) between the tantalum body 110 and the fifth surface S5 of the molded portion 150 satisfies the above-described range, the tantalum body 110 inside the molded portion 150 may be disposed as far as possible to maximize capacity.
The present disclosure also relates to a manufacturing method of a tantalum capacitor.
FIGS. 7A to 7E are views illustrating a manufacturing method of the tantalum capacitor 300 according to an exemplary embodiment of the present disclosure.
Referring to FIGS. 7A to 7E, the manufacturing method of the tantalum capacitor 300 includes operations of: mounting a tantalum capacitor 300, which includes a tantalum body 310 having a tantalum wire 320 exposed from one surface thereof, on the anode lead frame 330, which includes the anode terminal 332 and the anode connection member 331, and the cathode lead frame 340; and cutting the anode terminal 332, the anode connection member 331, and the tantalum wire 320.
In an exemplary embodiment of the present disclosure, the manufacturing method of the tantalum capacitor of the present disclosure may further include an operation of forming an anode lead frame and a cathode lead frame including an anode electrode terminal and an anode electrode connection member before the operation of mounting the tantalum capacitor.
In another exemplary embodiment of the present disclosure, the manufacturing method of the tantalum capacitor of the present disclosure may further include an operation of bonding the anode connection member and the tantalum wire after the operation of mounting the tantalum capacitor.
Hereinafter, a method of manufacturing a tantalum capacitor according to the present invention will be described in detail with reference to FIGS. 7A to 7E.
FIGS. 7A and 7B illustrate operations of forming the anode lead frame 330 and the cathode lead frame 340. The manufacturing method of the tantalum capacitor 300 according to the present disclosure may include an operation of forming an anode lead frame 330 by combining the anode terminal 332 and the anode connection member 331. In this case, a conductive adhesive layer 360 may be formed on the cathode lead frame 340 as necessary. In the present embodiment, a method of separately manufacturing and then combining the anode connection member 331 and the anode terminal 332 is used, but this is not essential, for example, the anode connection member 331 and the anode terminal 332 may be manufactured integrally. In addition, for curing the conductive adhesive layer 360, a process of curing at a temperature of about 100 to 200° C. may also be performed thereafter. The anode connection member 331, the anode terminal 332, and the cathode lead frame 340 may be manufactured using a conductive metal such as a nickel/iron alloy, or the like, but are not limited thereto.
When the anode lead frame 330 and the cathode lead frame 340 are prepared, as shown in FIG. 7C, the tantalum capacitor 300 in which the tantalum wire 320 is disposed on one surface thereof may be mounted on the upper surfaces of the anode lead frame 330 and the cathode lead frame 340. In this case, the anode lead frame 330 and the cathode lead frame 340 may be horizontally disposed to face each other. In addition, heat-resistant tapes may be attached to the lower surfaces of the anode lead frame 330 and the cathode lead frame 340 to be connected to each other. The heat-resistant tape is to prevent contamination of the surfaces of the anode lead frame 330 and the cathode lead frame 340 in a subsequent molding process.
Next, the anode connection member 331 and the tantalum wire 320 are bonded. In this case, the tantalum wire 320 and the anode connection member 331 may be bonded, while the tantalum wire 320 contacts the anode connection member 331 of the anode lead frame 330. A bonding method is not particularly limited, and may be attached by, for example, spot welding or laser welding or applying a conductive adhesive.
When the anode connection member 331 and the tantalum wire 320 are bonded, the tantalum wire 320, the anode connection member 331, and the anode terminal 332 are cut together. FIG. 7D is a view showing the cutting operation. Referring to FIG. 7D, after a cutting mask, a cutting line, or the like is disposed on the tantalum wire 320 connected to the anode connection member 331, cutting is performed using a blade, a dicing saw, a laser cutter, or the like, or using a method of cutting by inputting coordinates to be cut into a cutting device. A cutting position can be appropriately adjusted according to the capacity and size of the desired chip.
Next, as shown in FIG. 7E, a molded portion 250 is formed to surround the tantalum body 310 and the tantalum wire 320, and such that one surface of the anode lead frame 330 and the cathode lead frame 340 is exposed externally. The molded portion 250 serves to protect the tantalum wire 320 and the tantalum body 310 from the outside.
When the molded portion 250 is formed, a heat-resistant tape attached to the lower surfaces of the anode lead frame 330 and the cathode lead frame 340 is removed.
Through the above-described process, it is possible to manufacture a tantalum capacitor 300 according to an exemplary embodiment of the present disclosure.
Table 1 below compares a tantalum capacitor according to an exemplary embodiment of the present disclosure and a tantalum capacitor manufactured by the conventional method.
TABLE 1
Comparative
[Unit of volume: mm3]
Example
Example
Volume of a tantalum body
1.28
1.51
Increase rate of a volume of a tantalum
—
17.6%
body
Volume of a molded portion
2.98
2.98
v1/v2
42%
50%
In Table 1 above, in Comparative Example, a tantalum capacitor having a 2012 size is used, and v1/v2 shows a ratio (v1/v2) of the volume (v1) of a tantalum body to the volume (v2) of a molded portion in which the tantalum body is embedded. In addition, in the case of the Example, the molded portion was prepared using the same material as the Comparative Example, except that 0.2 mm thereof was cut from an end portion of the tantalum wire so that a length of the anode connection member in the X direction was 0.15 mm.
Referring to Table 1, it can be seen that a volume of a tantalum body significantly increases although the volume of an entire chip does not increase, and thus, it can be seen that a volume (v1/v2) substantially occupied by a capacitance portion is improved.
FIG. 8 shows that a breakdown voltage (BDV) of the above-described Examples and Comparative Examples. The breakdown voltage (BDV) was measured using a measuring device (manufactured by HP, a 4156B Precision Semiconductor Parameter Analyzer) under the condition of 100 mA compliance [0.2V/s]. Referring to FIG. 8, it can be seen that unlike in the Comparative Example, in the Example, excellent breakdown voltage (BDV) characteristics are exhibited.
As set forth above, according to an exemplary embodiment of the present disclosure, it is possible to provide a high-capacity tantalum capacitor by increasing an effective volume of the tantalum body.
According to another exemplary embodiment of the present disclosure, it is possible to provide a tantalum capacitor having excellent mechanical reliability by increasing adhesion of anode and cathode lead frames.
According to another exemplary embodiment of the present disclosure, a withstand voltage and a breakdown voltage of the tantalum capacitor may be increased by increasing a volume of the tantalum body.
According to another exemplary embodiment of the present disclosure, ESR of the tantalum capacitor can be reduced by reducing an electrical signal length.
However, various and advantageous advantages and effects of the present invention are not limited to the above description, and will be more readily understood in the course of describing specific embodiments of the present disclosure.
While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the spirit and scope of the present disclosure as defined by the appended claims.
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16876343
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samsung electro-mechanics co., ltd.
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USA
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B2
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Utility Patent Grant (with pre-grant publication) issued on or after January 2, 2001.
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Open
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Apr 27th, 2022 09:11AM
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Apr 27th, 2022 09:11AM
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Samsung
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krx:005930
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Samsung
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Apr 26th, 2022 12:00AM
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Feb 27th, 2020 12:00AM
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https://www.uspto.gov?id=US11315879-20220426
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Package substrate and multi-chip package including the same
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A package substrate, including a substrate, a first structure disposed on the substrate and having a first through-portion, a first wiring layer disposed in the first through-portion on the substrate, a first insulating layer disposed in the first through-portion on the substrate and covering at least a portion of the first wiring layer, and a second wiring layer disposed on the first insulating layer, and a multi-chip package, including the package substrate, are provided.
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11315879
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1. A package substrate comprising:
a substrate;
a first structure disposed on the substrate and having a first through-portion;
a first wiring layer disposed in the first through-portion on the substrate;
a first insulating layer disposed in the first through-portion on the substrate and covering at least a portion of the first wiring layer;
a second wiring layer disposed on the first insulating layer; and
a fourth wiring layer disposed on an external side of the first structure on the substrate,
wherein the first and fourth wiring layers are disposed on levels corresponding to each other.
2. The package substrate of claim 1, further comprising:
a second structure disposed on the first structure and having a second through-portion;
a second insulating layer disposed in the second through-portion on the first insulating layer; and
a third wiring layer disposed on the second insulating layer,
wherein the second wiring layer is disposed in the second through-portion on the first insulating layer, and
the second insulating layer covers at least a portion of the second wiring layer.
3. The package substrate of claim 2, wherein each of the first and second structures include a solder resist.
4. The package substrate of claim 2, wherein the second structure has a planar area less than a planar area of the first structure.
5. The package substrate of claim 2, wherein internal wall surfaces of the first and second through-portions have a step with respect to each other.
6. The package substrate of claim 4, wherein the second through-portion has a planar area larger than a planar area of the first through-portion.
7. The package substrate of claim 2, further comprising:
a first wiring via layer penetrating through the first insulating layer in the first through-portion and connecting the first and second wiring layers to each other; and
a second wiring via layer penetrating through the second insulating layer in the second through-portion and connecting the second and third wiring layers to each other.
8. The package substrate of claim 2, wherein the third wiring layer includes a plurality of first pads having a first pitch,
the fourth wiring layer includes a plurality of second pads having a second pitch, and
the first pitch is less than the second pitch.
9. The package substrate of claim 1, wherein the first structure includes a dam-shaped structure, and
the first insulating layer is disposed inside the dam-shaped structure and is spaced apart from a region outside the dam-shaped structure.
10. A multi-chip package comprising:
a package substrate including a substrate, a first structure disposed on the substrate and having a first through-portion, a first wiring layer disposed in the first through-portion on the substrate, a first insulating layer disposed in the first through-portion on the substrate and covering at least a portion of the first wiring layer, a second wiring layer disposed on the first insulating layer, and a fourth wiring layer disposed on an external side of the first structure on the substrate, wherein the first and fourth wiring layers are disposed on levels corresponding to each other;
a first semiconductor chip disposed on the package substrate and having first connection pads; and
a second semiconductor chip disposed near the first semiconductor chip on the package substrate and having second connection pads,
wherein at least one of the first connection pads and at least one of the second connection pads are connected to each other through the first wiring layer.
11. The multi-chip package of claim 10, wherein in a plan view of the multi-chip package, at least a portion of each of the first and second semiconductor chips overlaps at least a portion of the first wiring layer.
12. The multi-chip package of claim 10, wherein the package substrate further includes a second structure disposed on the first structure and having a second through-portion, a second insulating layer disposed in the second through-portion on the first insulating layer, and a third wiring layer disposed on the second insulating layer,
the second wiring layer is disposed in the second through-portion on the first insulating layer, and
the second insulating layer covers at least a portion of the second wiring layer.
13. The multi-chip package of claim 10, wherein in a plan view of the multi-chip package, at least a portion of each of the first and second semiconductor chips overlaps at least a portion of the fourth wiring layer.
14. The multi-chip package of claim 12, wherein the third wiring layer includes a plurality of first pads having a first pitch,
the fourth wiring layer includes a plurality of second pads having a second pitch, and
the first pitch is less than the second pitch.
15. The multi-chip package of claim 14, wherein at least one of the first connection pads is connected to at least one of the first pads through a first connection member, and at least one of the first connection pads is connected to at least one of the second pads through a second connection member,
at least one of the second connection pads is connected to at least one of the first pads through a third connection member, and at least one of the second connection pads is connected to at least one of the second pads through a fourth connection member, and
each of the first to fourth connection members includes at least one of a metal bump and an electrical connection member.
16. The multi-chip package of claim 10, wherein the first structure includes a dam-shaped structure, and
the first insulating layer is disposed inside the dam-shaped structure and is spaced apart from a region outside the dam-shaped structure.
17. A multi-chip package comprising:
a package substrate comprising:
a substrate;
a dam-shaped structure disposed on the substrate;
first patterns disposed inside the dam-shaped structure and on the substrate;
second patterns disposed outside the dam-shaped structure and on the substrate;
an insulating layer covering the first patterns;
a wiring layer disposed on the first insulating layer; and
a via layer disposed in the first insulating layer and connecting the first patterns to the wiring layer,
a first semiconductor chip disposed on the package substrate and having first connection pads; and
a second semiconductor chip disposed near the first semiconductor chip on the package substrate and having second connection pads,
wherein at least one of the first connection pads and at least one of the second connection pads are connected to each other through the first wiring layer, and
a portion of the first semiconductor chip and the second semiconductor chip overlaps at least a portion of the second patterns in a stacking direction of the dam-shaped structure and the substrate.
18. The multi-chip package of claim 17, wherein the insulating layer is composed of a photosensitive insulating material.
19. The multi-chip package of claim 17, wherein the insulating layer covers only the first patterns among the first patterns and the second patterns.
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19
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CROSS-REFERENCE TO RELATED APPLICATION(S)
This application claims the benefit under 35 USC 119 (a) of Korean Patent Application No. 10-2019-0163279 filed on Dec. 10, 2019 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.
TECHNICAL FIELD
The present disclosure relates to a package substrate and a multi-chip package including the same.
BACKGROUND
As compared with a case in which an entire system chip is manufactured using a single silicon die, in a case in which a die is divided into chiplets, manufacturing costs of chips may be further reduced and disposal costs resulting from poor yield may also be reduced. With the recent trend for chiplets, technologies for interconnection between chiplets have emerged. For example, a substrate including a silicon interposer, a substrate including a silicon-based interconnect bridge, capable of achieving a die-to-die a die-to-die electrical connection, and the like, have been developed. However, such technologies are required to manufacture expensive silicon interconnect dies. Additionally, in the case of a silicon-based interconnect bridge, a reliability issue arises due to a coefficient of thermal expansion (CTE) mismatch between a silicon material of the bridge and an organic material of a substrate.
SUMMARY
An aspect of the present disclosure is to provide a package substrate, capable of providing a relatively cheap multi-chip interconnection, and a multi-chip package including the same.
Another aspect of the present disclosure is to provide a package substrate, capable of lowering a yield reduction risk, and a multi-chip package including the same.
Another aspect of the present disclosure is to provide a package substrate, having a high degree of freedom in wiring design, and a multi-chip package including the same.
Another aspect of the present disclosure is to provide a package substrate having improved reliability, advantageous for bending control, and a multi-chip package including the same.
Another aspect of the present disclosure is to provide a package substrate, capable of forming a slim structure, and a multi-chip package including the same.
According to an aspect of the present disclosure, a fine circuit is implemented by forming a dam-shaped structure on a structure and sequentially forming a wiring layer, an insulating layer, and the like, in a through-portion provided through the structure.
For example, a package substrate includes a substrate, a first structure disposed on the substrate and having a first through-portion, a first wiring layer disposed in the first through-portion on the substrate, a first insulating layer disposed in the first through-portion on the substrate and covering at least a portion of the first wiring layer, and a second wiring layer disposed on the first insulating layer.
For example, a multi-chip package includes a package substrate including a substrate, a first structure disposed on the substrate and having a first through-portion, a first wiring layer disposed in the first through-portion on the substrate, a first insulating layer disposed in the first through-portion on the substrate and covering at least a portion of the first wiring layer, and a second wiring layer disposed on the first insulating layer, a first semiconductor chip disposed on the package substrate and having first connection pads, and a second semiconductor chip disposed around the first semiconductor chip on the package substrate and having second connection pads. At least one of the first connection pads and at least one of the second connection pads are electrically connected to each other through the first wiring layer.
For example, a package substrate includes a substrate, a dam-shaped structure disposed on the substrate, first patterns disposed inside the dam-shaped structure and on the substrate, second patterns disposed outside the dam-shaped structure and on the substrate, an insulating layer covering only the first patterns among the first patterns and the second patterns, a wiring layer disposed on the first insulating layer, and a via layer disposed in the first insulating layer and connecting the first patterns to the wiring layer.
BRIEF DESCRIPTION OF DRAWINGS
The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a schematic block diagram illustrating an example of an electronic device system;
FIG. 2 is a schematic perspective view illustrating an example of an electronic device;
FIG. 3 is a schematic cross-sectional view of a multi-chip package according to an example;
FIG. 4 is a schematic plan view of a package substrate according to the example applied to the multi-chip package in FIG. 3, when viewed from above; and
FIGS. 5 and 6 are schematic process diagrams illustrating an example of manufacturing a package substrate according to the example applied to the multi-chip package in FIG. 3.
DETAILED DESCRIPTION
Hereinafter, embodiments of the present disclosure will be described as follows with reference to the attached drawings.
FIG. 1 is a schematic block diagram illustrating an example of an electronic device system.
Referring to FIG. 1, an electronic device 1000 accommodates a mainboard 1010. The mainboard 1010 may include chip related components 1020, network related components 1030, other components 1040, and the like, physically or electrically connected thereto. These components may be connected to others to be described below to form various signal lines 1090.
The chip related components 1020 may include a memory chip such as a volatile memory (for example, a dynamic random access memory (DRAM)), a non-volatile memory (for example, a read only memory (ROM)), a flash memory, or the like; an application processor chip such as a central processor (for example, a central processing unit (CPU)), a graphics processor (for example, a graphics processing unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like; and a logic chip such as an analog-to-digital (ADC) converter, an application-specific integrated circuit (ASIC), or the like. However, the chip related components 1020 are not limited thereto, but may also include other types of chip related components. In addition, the chip related components 1020 may be combined with each other. The chip related components 1020 may be in the form of a package including the above-described chips or electronic components.
The network related components 1030 may include protocols such as wireless fidelity (Wi-Fi) (Institute of Electrical And Electronics Engineers (IEEE) 802.11 family, or the like), worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, or the like), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high speed packet access+(HSPA+), high speed downlink packet access+(HSDPA+), high speed uplink packet access+(HSUPA+), enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G, 4G, and 5G protocols, and any other wireless and wired protocols, designated after the abovementioned protocols. However, the network related components 1030 are not limited thereto, but may also include a variety of other wireless or wired standards or protocols. In addition, the network related components 1030 may be combined with each other, together with the chip related components 1020 described above.
Other components 1040 may include a high frequency inductor, a ferrite inductor, a power inductor, ferrite beads, a low temperature co-fired ceramic (LTCC), an electromagnetic interference (EMI) filter, a multilayer ceramic capacitor (MLCC), or the like. However, other components 1040 are not limited thereto, but may also include passive components used for various other purposes, or the like. In addition, other components 1040 may be combined with each other, together with the chip related components 1020 or the network related components 1030 described above.
Depending on a type of the electronic device 1000, the electronic device 1000 may include other components that may or may not be physically or electrically connected to the mainboard 1010. These other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not illustrated), a video codec (not illustrated), a power amplifier (not illustrated), a compass (not illustrated), an accelerometer (not illustrated), a gyroscope (not illustrated), a speaker (not illustrated), a mass storage unit (for example, a hard disk drive) (not illustrated), a compact disk (CD) drive (not illustrated), a digital versatile disk (DVD) drive (not illustrated), or the like. However, these other components are not limited thereto, but may also include other components used for various purposes depending on a type of electronic device 1000, or the like.
The electronic device 1000 may be a smartphone, a personal digital assistant (PDA), a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game machine, a smartwatch, an automotive component, or the like. However, the electronic device 1000 is not limited thereto, but may be any other electronic device processing data.
FIG. 2 is a schematic perspective view illustrating an example of an electronic device.
Referring to the drawings, an electronic device may be, for example, a smartphone 1100. The main board 1110 may be accommodated in the smartphone 1100, and various electronic components 1120 may be physically and/or electrically connected to the main board 1110. In addition, other electronic components, such as the camera module 1130 and/or the speaker 1140, which may or may not be physically and/or electrically connected to the main board 1110 may be accommodated therein. A portion of the electronic components 1120 may be the above-described chip related components, for example, a semiconductor package 1121, but are not limited thereto. The semiconductor package 1121 may be a surface in which a semiconductor chip or a passive component is mounted on a package substrate in a package substrate form, but is not limited thereto. The electronic device is not necessarily limited to the smartphone 1100, but may be other electronic devices as described above.
Referring to FIG. 2, an electronic device may be, for example, a smartphone 1100. The mainboard 1110 may be accommodated in the smartphone 1100, and various electronic components 1120 may be physically and/or electrically connected to the mainboard 1110. In addition, other electronic components, such as a camera module 1130 and/or a speaker 1140, which may or may not be physically and/or electrically connected to the mainboard 1110, may be accommodated therein. A portion of the electronic components 1120 may be the above-described chip-related components, for example, a semiconductor package 1121, but are not limited thereto. The semiconductor package 1121 may be a surface in which multiple chips are mounted on a package substrate in a package substrate form, but is not limited thereto. The electronic device is not necessarily limited to the smartphone 1100, but may be other electronic devices as described above.
FIG. 3 is a schematic cross-sectional view of a multi-chip package according to an example.
FIG. 4 is a schematic plan view of a package substrate according to the example applied to the multi-chip package in FIG. 3, when viewed from above.
Referring to FIGS. 3 and 4, a multi-chip package 500 according to an example includes a package substrate 100, a first semiconductor chip 310 disposed on the package substrate 100, and a second semiconductor chip 320 disposed around the first semiconductor chip 310 on the package substrate 100. The package substrate 100 includes a substrate 110, a structure 120 disposed on the substrate 110 and having a through-portion 120H, and an insulating layer 130, a wiring layer 140, and a wiring via layer 150 disposed in the through-portion 120H on the substrate 110. The first and second semiconductor chips 310 and 320 may each be electrically connected to the wiring layer 140 of the package substrate 100, and may be electrically connected to each other through the wiring layer 140.
As described above, with the recent trend for chiplets, technologies for interconnection between chiplets have emerged. For example, a substrate including a silicon interposer, a substrate including a silicon-based interconnect bridge, capable of achieving a die-to-die electrical connection, and the like, have been developed. However, such technologies are required to manufacture expensive silicon interconnect dies. Additionally, in the case of a silicon-based interconnect bridge, a reliability issue arises due to a coefficient of thermal expansion (CTE) mismatch between a silicon material of the bridge and an organic material of a substrate.
On the other hand, the multi-chip package 500 according to an example may provide an interconnection between multiple chips through the package substrate 100 providing an organic bridge circuit. For example, the package substrate 100 according to an example may be fabricated by forming a dam-shaped structure 120 on the substrate 110 and sequentially forming a wiring layer 140, an insulating layer 130, and the like, in the through-portion 120H provided through the structure 120. In this case, rather than a silicon-based process, an organic-based process may basically be performed to reduce costs and to lower a process difficulty level. In addition, since an additional bridge die does not need to be inserted, a yield reduction risk may be lowered. In addition, a material of the insulating layer 130 may be a liquid photosensitive material, such that a fine circuit may be implemented and a degree of freedom in design may be high. Accordingly, a locally fine circuit for interconnection between multiple chips may easily be provided when it is required. In addition, heterogeneous materials may be applied only locally and there is no cavity process for inserting an additional bridge die, or the like, which is advantageous for bending control. In addition, an additional interposer substrate may be omitted, which is advantageous for a slim structure of a product. In addition, since the wiring layer 140 and the like are integrated with the substrate 110, a circuit wiring in the substrate 110 may be easily connected to the wiring layer 140 to reduce signal loss.
In the package substrate 100 according to the example structure 120, each of the insulating layer 130, the wiring layer 140, and the wiring via layer 150 may include a plurality of layers. For example, the package substrate 100 according to an example may include a first structure 121 disposed on the substrate 100 and having a first through-portion 121H, a second structure 122 disposed on the first structure 121 and having a second through-portion 122H, a first wiring layer 141 disposed in the first through-portion 121H on the substrate 100, a first insulating layer 131 disposed in the first through-portion 121H on the substrate 100 and covering at least a portion of the first wiring layer 141, a second wiring layer 142 disposed in a second through-portion 122H on the first insulating layer 131, a first wiring via layer 151 penetrating through the first insulating layer 131 in the first through-portion 121H and connecting the first and second wiring layers 141 and 142 to each other, a second insulating layer 132 disposed in the second through-portion on the first insulating layer 131 and covering at least a portion of the second wiring layer 142, a third wiring layer 143 disposed on the second insulating layer 132, and a second wiring via layer 152 penetrating through the second insulating layer 132 in the second through-portion 122H and connecting second and third wiring layers 142 and 143 to each other. As described, the number of layers in the fine circuit may be adjusted, as needed.
Meanwhile, the package substrate 100 according to an example may further include a fourth wiring layer 145 disposed on an external side of the structure 120, for example, an external side of the first structure 121 on the substrate 110. The fourth wiring layer 145 may be disposed on a level corresponding to a level of the first wiring layer 141. The fourth wiring layer 145 may be an additional circuit rather than a bridge circuit. At least a portion of the fourth wiring layer 145 may be electrically connected to at least a portion of the first wiring layer 141. Each of the first and second semiconductor chips 310 and 320 may be electrically connected to at least a portion of the fourth wiring layer 145. As described above, since the degree of freedom in design is high, a typical wiring circuit may be designed on the substrate 110 independently of the bridge circuit. In this case, as a non-limiting example, the third wiring layer 143, an uppermost wiring layer of the wiring layer 140, may include a plurality of first pads 143P having a first pitch P1, and the fourth wiring layer 145 may include a plurality of second pads 145P having a second pitch P2, and the first pitch P1 may be less than the second pitch P2. For example, the plurality of first pads 143P may be fine circuits having a finer pitch than the plurality of second pads 145P. Such a relationship may also be applied to other wiring layers in the wiring layer 140.
Hereinafter, a multi-chip package according to an example and a package substrate according to one example, included in the multi-chip package, will be described in detail with reference to drawings.
The substrate 100 may be a multilayer printed circuit board (PCB). The printed circuit board (PCB) may be a cored PCB or a coreless PCB. As a non-limiting example, the substrate 100 may be a ball grid array (BGA) type PCB. The substrate 100 may include a plurality of insulating layers, a plurality of wiring layers, and a plurality of via layers. The number of layers of the insulating layers, the wiring layers, and the via layers is not necessarily limited, and each of the insulating layers, the wiring layers, and the via layers may include multiple layers or a single layer, depending on design.
A material of the insulating layer may be an insulating material. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or materials including reinforcements such as glass fiber, glass cloth, glass fabric, and/or inorganic fillers, together with these, such as copper clad laminate (CCL), flexible copper clad laminate (FCCL), prepreg, Ajinomoto Build-up Film (ABF), photoimageable dielectric (PID), or the like. However, the insulating material is not limited thereto, and a glass plate or a ceramic plate may be used as a material of a specific insulating layer, for example, a core layer. As necessary, liquid crystal polymer (LCP) having low dielectric loss may be used. When a plurality of insulating layers are used, a material of each of the insulating layers may be the same or different from each other.
A material of the wiring layers may be a metal material. In this case, the metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, or the like. The wiring layers may serve to perform various functions depending on a design of a layer of interest. For example, the wiring layers may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. In this case, the signal (S) pattern may include various signals except for the ground (GND) pattern, the power (PWR) pattern, and the like, for example, a data signal, and the like. These patterns may each include a line pattern, a plane pattern, and/or a pad pattern.
A material of the via layer may also be a metal material. In this case, the metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, or the like. A wiring via of each of the via layers may be completely filled with a metal material, or the metal material may be formed along a wall of a via hole. In addition, known shapes such as a tapered shape, an hourglass shape, a cylindrical shape, and the like, may all be applied thereto. The via layers may serve to perform various functions depending on a design of a layer of interest. For example, each of the wiring vias may include a wiring via for signal connection, a wiring via for ground connection, a wiring via for power connection, or the like.
The structure 120 may include first and second structures 121 and 122. The first and second structures 121 and 122 may have first and second through-portions 121H and 122H, respectively. The first and second through-portions 121H and 122H may be connected to each other to constitute a through-portion 120H. A material of the first and second structures 121 and 122 is not necessarily limited, and may be any material as long as it serves as a damp. As a non-limiting example, each of the first and second structures 121 and 122 may include a solder resist. In this case, since each of the first and second structures 121 and 122 may be easily patterned to have a desired shape, the first and second through-portions 121H and 122H may be more easily implemented. However, the present disclosure is not limited thereto, and the first and second structures 121 and 122 may include other known insulating materials. As necessary, the first and second structures 121 and 122 may include a metal material or a ceramic material.
The structure 120 may have a staircase shape when including a plurality of layers. For example, the second structure 122 may have a planar area smaller than an area of the first structure 121. Therefore, an internal wall surface of the first through-portions 121H and an internal wall surface of the second through-portions 122H may have a step with respect to each other. In addition, an external side surface of the first structure 121 and an external side surface of the second structure 122 may also have a step with respect to each other. In this regard, the second through-portions 122H may have a planar area larger than an area of the first through-portions 121H. When the structure 120 is implemented to include multiple layers through such staircase implementation, alignment may be more easily performed and the multilayer insulation layer 130, the wiring layer 140, and the wiring via layer 150 may be sequentially formed more easily.
The insulating layer 130 may include first and second insulating layers 131 and 132. The first and second insulating layers 131 and 132 may include an insulating material and, for example, a photoimageable dielectric (PID), a photosensitive insulating material. The photoimageable dielectric (PID) may be provided in a liquid state to be cured, which allows a fine circuit to be easily implemented. A boundary between the first and second insulating layers 131 and 132 may be apparent or may not be apparent.
The wiring layer 140 may include first to third wiring layers 141, 142, and 143. The first to third wiring layers 141, 142, and 143 may include a metal material. The metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, or the like. The first to third wiring layers 141, 142, and 143 may serve to perform various functions depending on a design of a layer of interest. For example, the first to third wiring layers 141, 142, and 143 may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. In this case, the signal (S) pattern may include various signals except for the ground (GND) pattern, the power (PWR) pattern, and the like, for example, a data signal, and the like. These patterns may each include a line pattern, a plane pattern, and/or a pad pattern. The fourth wiring layer 145 may also include the above-mentioned metal material, and may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. In addition, the fourth wiring layer 145 may include a line pattern, a plane pattern, and/or a pad pattern. The patterns of the first to third wiring layers 141, 142, and 143 may be formed as fine circuits having density higher than density of the patterns of the fourth wiring layer 145, respectively.
The wiring via layer 150 may include first and second wiring via layers 151 and 152. The first and second wiring via layers 151 and 152 may include a metal material. The metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, or the like. A wiring via of each of the first and second wiring via layers 151 and 152 may be completely filled with a metal material, or the metal material may be formed along a wall surface of a via hole. In addition, known shapes such as a tapered shape, an hourglass shape, a cylindrical shape, and the like, may all be applied thereto. The first and second wiring via layers 151 and 152 may also serve to perform various functions depending on a design of a layer of interest. For example, each of the first and second wiring via layers 151 and 152 may include a wiring via for signal connection, a wiring via for ground connection, a wiring via for power connection, or the like.
The first semiconductor chip 310 may be a die having a form of an integrated circuit (IC) in which hundreds to millions of or more devices are integrated in a single chip. In this case, a base material constituting the body may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits may be formed in the body. A first connection pad 310P of the first semiconductor chip 310 is provided to electrically connect the first semiconductor chip 310 to another component, and a material forming the first connection pad 310P may be a metal material such as copper (Cu), aluminum (Al), or the like, but are not limited thereto. A passivation layer may be formed on the body to expose the first connection pad 310P. The passivation layer may be an oxide layer, a nitride layer, or the like, or may be a double layer of the oxide layer and the nitride layer. An insulating layer, or the like, may be further disposed in other necessary locations. As necessary, the first semiconductor chip 310 may be a chip-scale packaged die in which a redistribution layer is formed on the body to redistribute the first connection pad 310P.
The second semiconductor chip 320 may also be a die having a form of an integrated circuit (IC) in which hundreds to millions of or more devices are integrated in a single chip. As necessary, the second semiconductor chip 320 may have a structure in which a plurality of integrated circuits (ICs) are stacked. The stacked integrated circuits IC may be electrically connected to each other through a through-silicon via (TSV). The second semiconductor chip 320 may also have a second connection pad 122P to be electrically connected to another component, and may be further provided with a passivation layer, an insulating layer, or the like. As necessary, the second semiconductor chip 320 may also be a chip-scale packaged die.
As a non-limiting example, the first semiconductor chip 310 may be an application specific integrated circuit (ASIC). Alternatively, the first semiconductor chip 310 may be a field programmable gate array (FPGA). Alternatively, the first semiconductor chip 310 may be a chipset of an application specific integrated circuit (ASIC) and a field programmable gate array (FPGA). Alternatively, the first semiconductor chip 310 may be a graphics processing unit (GPU). Alternatively, the first semiconductor chip 310 may be a chipset of an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), and a graphics processing unit (GPU). In addition, the second semiconductor chip 320 may be a stacked memory such as a high bandwidth memory (HBM). Each of the first and second semiconductor chips 310 and 320 may be a relatively expensive chip having tens to millions of or more I/Os, but is not limited thereto. Each of the first and second semiconductor chips 310 and 320 may include a plurality of semiconductor chips. In this case, in a fine circuit region provided through the structure 120, the insulating layer 130, the wiring layer 140, and the wiring via layer 150 of the package substrate 100, the plurality of semiconductor chips may be formed locally and independently of each other.
At least a portion of the first semiconductor chip 310 may be disposed to overlap at least a portion of the wiring layer 140, for example, the first to third wiring layers 141, 142, and 143, when viewed from above. In addition, at least a portion of the first semiconductor chip 310 may be disposed to overlap at least a portion of the fourth wiring layer 145, when viewed from above. In this case, at least one of the plurality of first connection pads 310P of the first semiconductor chip 310 may be connected to at least one of the plurality of third pads 143P of the third wiring layer 143 through the first connection members 311 and 313. In addition, at least one of the plurality of first connection pads 310P of the first semiconductor chip 310 may be connected to at least one of the plurality of third pads 145P of the fourth wiring layer 145 through the second connection members 312 and 314.
At least a portion of the second semiconductor chip 320 may be disposed to overlap at least a portion of the wiring layer 140, for example, the first to third wiring layers 141, 142, and 143, when viewed from above. In addition, at least a portion of the second semiconductor chip 320 may be disposed to overlap at least a portion of the fourth wiring layer 145, when viewed from above. In this case, at least one of the plurality of second connection pads 320P of the second semiconductor chip 320 may be connected to at least one of the plurality of third pads 143P of the third wiring layer 143 through the third connection members 321 and 323. In addition, at least one of the plurality of second connection pads 320P of the second semiconductor chip 320 may be connected to at least one of the plurality of third pads 145P of the fourth wiring layer 145 through the fourth connection members 322 and 324.
The first to fourth connection members 311, 312, 313, 314, 321, 322, 323, and 324 may include at least one of first to fourth metal bumps 311, 312, 321, and 322 and at least one of first to fourth electrical connection metals 313, 314, 323, and 324, respectively. Each of the first to fourth connection members 311, 312, 313, 314, 321, 322, 323, and 324 may includes a plurality of connection members, and a pitch between the plurality of connection members may correspond to a pitch between a plurality of connected pads 143P and 145P. Each of the first to fourth metal bumps 311, 312, 321, and 322 may be a metal post including copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof, but a material thereof is not limited thereto. Each of the first to fourth electrical connection metals 313, 314, 323, and 324 may be formed of a solder, an alloy including a metal, having a low melting point, lower than a melting point of copper (Cu), for example, tin (Sn) or an alloy including tin (Sn), but is merely an example and the material is not limited thereto.
FIGS. 5 and 6 are schematic process diagrams illustrating an example of manufacturing a package substrate according to the example applied to the multi-chip package in FIG. 3.
Referring to FIG. 5, a substrate 110 is prepared. A first wiring layer 141 is formed on the substrate 110 using a plating process such as an additive process (AP), a semi-AP (SAP), a modified SAP (MSAP), tenting (TT), or the like. As necessary, a fourth wiring layer 145 is also formed in the same plating process. In this case, the first wiring layer 141 and the fourth wiring layer 145 may have the same or substantially the same thickness, and may be made of the same material. In addition, a structure 120 is formed on the substrate 110 by patterning performed through a photolithography process of a solder resist film, or patterning performed through a sandblasting, etching, or laser process of an ABF. The structure 120 may be formed of a plurality of layers depending on a design, and may be formed to include, for example, first and second structures 121 and 122. The order, in which the first and fourth wiring layers 141 and 145 and the structure 120 are formed, is not necessarily limited. The first and fourth wiring layers 141 and 145 may be formed first, and the structure 120 may be formed first. Next, a photosensitive insulating material, or the like, in a liquid state is applied to a first through-portion 121H of the first structure 121 and then cured to form a first insulating layer 131. Applying the photosensitive insulating material may be performed using various types of coating process. Next, a via hole 151v for forming a wiring via layer is formed in the first insulating layer 131 using a photolithography process or the like.
Referring to FIG. 6, a second wiring layer 142 is formed on the first insulating layer 131 by the above-mentioned plating process. In this case, the first wiring via layer 151 is also formed by filling the via hole 151v. Next, a photosensitive insulating material in a liquid state, or the like, is applied to the second through-portions 122H of the second structure 122 and then cured to form a second insulating layer 132. Applying the photosensitive insulating material may also be performed using various types of coating process. Next, a via hole for forming the second wiring via layer 152 is formed in the second insulating layer 132 using a photolithography process or the like. Then, a third wiring layer 143 is formed on the insulating layer 132 by the above-mentioned plating process. In this case, a second wiring via layer 152 is also formed by filling the via hole. Depending on the number of layers of the structure 120, a series of processes may be further repeated such that a fine circuit region is formed to have more multiple layers. As a result, the above-described package substrate 100 according to an example may be manufactured.
As described above, a package substrate, capable of providing a relatively cheap multi-chip interconnection, and a multi-chip package including the package substrate may be provided.
In addition, a package substrate, capable of lowering a yield reduction risk, and a multi-chip package including the package substrate may be provided.
In addition, a package substrate, having a high degree of freedom in wiring design, and a multi-chip package including the package substrate may be provided.
In addition, a package substrate having improved reliability, advantageous for bending control, and a multi-chip package including the package substrate may be provided.
In addition, a package substrate, capable of forming a slim structure, and a multi-chip package including the package substrate may be provided.
In the present disclosure, the terms “lower side”, “lower portion”, “lower surface,” and the like, have been used to indicate a direction toward a mounted surface of the electronic component package in relation to cross sections of the drawings, the terms “upper side”, “upper portion”, “upper surface,” and the like, have been used to indicate an opposite direction to the direction indicated by the terms “lower side”, “lower portion”, “lower surface,” and the like. However, these directions are defined for convenience of explanation only, and the claims are not particularly limited by the directions defined, as described above.
The meaning of a “connection” of a component to another component in the description includes an indirect connection through an adhesive layer as well as a direct connection between two components. In addition, “electrically connected” means including a physical connection and a physical disconnection. It can be understood that when an element is referred to as “first” and “second”, the element is not limited thereby. These terms may be used only for a purpose of distinguishing the element from the other elements, and may not limit the sequence or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the claims set forth herein. Similarly, a second element may also be referred to as a first element.
The term “an example embodiment” used herein does not always refer to the same example embodiment, and is provided to emphasize a particular feature or characteristic different from that of another example embodiment. However, example embodiments provided herein are considered to be able to be implemented by being combined in whole or in part one with another. For example, one element described in a particular example embodiment, even if it is not described in another example embodiment, may be understood as a description related to another example embodiment, unless an opposite or contradictory description is provided therein.
Terms used herein are used only in order to describe an example embodiment rather than to limit the present disclosure. In this case, singular forms include plural forms unless necessarily interpreted otherwise, based on a particular context.
While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present disclosure as defined by the appended claims.
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16803764
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samsung electro-mechanics co., ltd.
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USA
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B2
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Utility Patent Grant (with pre-grant publication) issued on or after January 2, 2001.
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Open
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Apr 27th, 2022 09:11AM
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Apr 27th, 2022 09:11AM
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Samsung
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krx:005930
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Samsung
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Apr 26th, 2022 12:00AM
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Dec 7th, 2018 12:00AM
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https://www.uspto.gov?id=US11315719-20220426
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Method of manufacturing a coil component
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A manufacturing method of a coil component includes: forming a plating resist on an internal insulating layer; forming a coil pattern and a lead pattern connected to the coil pattern and at least partially having a thickness smaller than that of the coil pattern by plating; removing the plating resist; and stacking a magnetic sheet on the internal insulating layer to form a body.
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11315719
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1. A method of manufacturing a coil component, the method comprising:
forming a plating resist on an internal insulating layer;
forming a coil pattern and a lead pattern connected to the coil pattern by plating, wherein at least a portion of the lead pattern has a thickness smaller than that of the coil pattern;
removing the plating resist; and
stacking a magnetic sheet on the internal insulating layer to form a body,
wherein the plating resist includes:
an opening pattern corresponding to the coil pattern;
a hollow pattern corresponding to the lead pattern and being in communication with the opening pattern; and
a cover portion at least partially covering the hollow pattern.
2. The manufacturing method of claim 1, wherein the cover portion extends parallel to a surface of the internal insulating layer and is spaced apart from the internal insulating layer.
3. The manufacturing method of claim 2, wherein the forming of the plating resist includes:
stacking a dry film on the internal insulating layer; and
performing exposure on the dry film several times while changing an exposure region.
4. The manufacturing method of claim 3, wherein the performing of exposure on the dry film several times includes:
performing exposure on a first region of the dry film using a first exposure energy; and
performing exposure on a second region of the dry film using a second exposure energy lower than the first exposure energy.
5. The manufacturing method of claim 1, further comprising, before the forming of the plating resist on the internal insulating layer, forming a seed layer on the internal insulating layer.
6. The manufacturing method of claim 5, further comprising, after the removing of the plating resist, selectively removing the seed layer so as to form a seed pattern corresponding to the coil pattern and the lead pattern.
7. The manufacturing method of claim 1, wherein the forming of the plating resist on the internal insulating layer includes:
forming a seed pattern corresponding to the coil pattern and the lead pattern on the internal insulating layer; and
forming the plating resist on the internal insulating layer on which the seed pattern is formed.
8. The manufacturing method of claim 7, wherein the forming of the coil pattern and the lead pattern by plating is performed by an anisotropic plating.
9. The manufacturing method of claim 1, wherein the forming of the coil pattern and the lead pattern by plating is performed by an anisotropic plating.
10. A method of manufacturing a coil component, the method comprising:
forming a plating resist on an internal insulating layer;
forming a coil pattern and a lead pattern connected to the coil pattern by plating, wherein at least a portion of the lead pattern has a thickness smaller than that of the coil pattern;
removing the plating resist; and
stacking a magnetic sheet on the internal insulating layer to form a body,
wherein the forming of the plating resist on the internal insulating layer includes:
forming a seed pattern corresponding to the coil pattern and the lead pattern on the internal insulating layer; and
forming the plating resist on the internal insulating layer on which the seed pattern is formed.
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10
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CROSS-REFERENCE TO RELATED APPLICATION(S)
This application claims the benefit of priority to Korean Patent Application No. 10-2018-0041462 filed on Apr. 10, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
BACKGROUND
1. Field
The present disclosure relates to a coil component and a method of manufacturing thereof.
2. Description of Related Art
An inductor, which is a type of coil component, is a representative passive element constituting an electronic circuit together with a resistor and a capacitor to remove noise.
A thin film type inductor may be manufactured by forming a coil pattern by plating, hardening a magnetic powder-resin composite in which magnetic powder particles and a resin are mixed with each other to manufacture a magnetic body, and forming external electrodes on outer surfaces of the magnetic body.
In accordance with recent trends toward increased complexation, multifunctionalization, slimness of a set, and further decreased thickness of the thin film type inductor as described above, research has been continuously conducted.
SUMMARY
An aspect of the present disclosure may provide a coil component and a method of manufacturing thereof capable of increasing binding force between a body and a coil part by forming a lead pattern to at least partially have a thickness smaller than that of a coil pattern.
According to an aspect of the present disclosure, a manufacturing method of a coil component may include: forming a plating resist on an internal insulating layer; forming a coil pattern and a lead pattern connected to the coil pattern and at least partially having a thickness smaller than that of the coil pattern by plating; removing the plating resist; and stacking a magnetic sheet on the internal insulating layer to form a body.
Here, the plating resist may include an opening pattern corresponding to the coil pattern and a hollow pattern corresponding to the lead pattern, being in communication with the opening pattern, and having an upper portion at least partially covered by a cover portion.
According to another aspect of the present disclosure, a coil component is obtained by the manufacturing method.
BRIEF DESCRIPTION OF DRAWINGS
The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a perspective view schematically illustrating a coil component according to an exemplary embodiment in the present disclosure;
FIG. 2 is a cross-sectional view taken along line I-I′ of FIG. 1; and
FIGS. 3 through 9 are views sequentially illustrating a manufacturing method of the coil component according to an exemplary embodiment in the present disclosure.
DETAILED DESCRIPTION
Hereinafter, exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.
In the accompanying drawings, an L direction refers to a first direction or a length direction, a W direction refers to a second direction or a width direction, and a T direction refers to a third direction or a thickness direction.
Hereinafter, a manufacturing method of a coil component according to an exemplary embodiment in the present disclosure will be described in detail with reference to the accompanying drawings. In describing an exemplary embodiment in the present disclosure with reference to the accompanying drawings, components that are the same as or correspond to each other will be denoted by the same reference numerals, and an overlapped description thereof will be omitted.
Coil Component
FIG. 1 is a perspective view schematically illustrating a coil component according to an exemplary embodiment in the present disclosure. FIG. 2 is a cross-sectional view taken along line I-I′ of FIG. 1.
Referring to FIGS. 1 and 2, a coil component 1000 according to the exemplary embodiment in the present disclosure may include a body 100, a coil part 200, external electrodes 300 and 400, an internal insulating layer 500, and an insulating film 600.
The body 100 may form an exterior of the coil component 1000 according to the present exemplary embodiment, and the coil part 200 may be embedded therein.
The body 100 may be formed in an entirely hexahedral shape.
Hereinafter, as an example, the first exemplary embodiment in the present disclosure will be described on the assumption that the body 100 has a hexahedral shape. However, a coil component including a body formed in a shape other than the hexahedral shape is not excluded in the scope of the present exemplary embodiment by the description.
The body 100 may have first and second surfaces opposing each other in the length (L) direction, third and fourth surfaces opposing each other in the width (W) direction, and fifth and sixth surfaces opposing each other in the thickness (T) direction. The first to fourth surfaces of the body 100 may correspond to wall surfaces of the body 100 connecting the fifth and sixth surfaces of the body 100 to each other. The wall surfaces of the body 100 may include the first and second surfaces corresponding to both end surfaces opposing each other and the third and fourth side surfaces corresponding to both side surfaces opposing each other.
For example, the body 100 may be formed so that the coil component 1000 in which external electrodes 300 and 400 to be described below are formed has a length of 2.0 mm, a width of 1.2 mm, and a thickness of 0.65 mm, but the body 100 is not limited thereto. Meanwhile, the above-mentioned numerical values of the length, the width, and the thickness of the coil component are values without considering tolerances and an actual length, an actual width, and an actual thickness of the coil component may be different from the numerical values described above by the tolerances.
The body 100 may contain a magnetic material and a resin. More specifically, the body may be formed by stacking one or more magnetic composite sheets (110 in FIG. 9) in which the magnetic material is dispersed in the resin. However, the body 100 may also have a different structure other than a structure in which the magnetic material is dispersed in the resin. For example, the body 100 may also be formed of a magnetic material such as ferrite.
The magnetic material may be ferrite or a metal magnetic powder.
As an example, the ferrite may be at least one selected from spinel type ferrite such as Mg—Zn based ferrite, Mn—Zn based ferrite, Mn—Mg based ferrite, Cu—Zn based ferrite, Mg—Mn—Sr based ferrite, and Ni—Zn based ferrite; hexagonal ferrite such as Ba—Zn based ferrite, Ba—Mg based ferrite, Ba—Ni based ferrite, Ba—Co based ferrite, and Ba—Ni—Co based ferrite; garnet type ferrite such as Y based ferrite; and Li based ferrite.
The metal magnetic powder may contain one or more selected from the group consisting of iron (Fe), silicon (Si), chromium (Cr), cobalt (Co), molybdenum (Mo), aluminum (Al), niobium (Nb), copper (Cu), and nickel (Ni). For example, the metal magnetic powder may be at least one of pure iron powder, Fe—Si based alloy powder, Fe—Si—Al based alloy powder, Fe—Ni based alloy powder, Fe—Ni—Mo based alloy powder, Fe—Ni—Mo—Cu based alloy powder, Fe—Co based alloy powder, Fe—Ni—Co based alloy powder, Fe—Cr based alloy powder, Fe—Cr—Si based alloy powder, Fe—Si—Cu—Nb based alloy powder, Fe—Ni—Cr based alloy powder, and Fe—Cr—Al based alloy powder.
The metal magnetic powder may be amorphous or crystalline. For example, the metal magnetic powder may be Fe—Si—B—Cr based amorphous alloy powder, but is not necessarily limited thereto.
The ferrite and the metal magnetic powder may each have an average diameter of about 0.1 μm to 30 μm, but are not limited thereto.
The body 100 may contain two or more kinds of magnetic materials dispersed in the resin. Here, the phrase “different kinds of magnetic materials” means that the magnetic materials dispersed in the resin are distinguished from each other in any one of an average diameter, a composition, crystallinity, and a shape thereof.
The resin may include one or a mixture of epoxy, polyimide, a liquid crystal polymer (LCP), and the like, but is not limited thereto.
The body 100 may include a core penetrating through a coil part 200 and an internal insulating layer 500 to be described below. The core may be formed by filling the magnetic composite sheet (110 in FIG. 9) in a through hole formed in the coil part 200 and the internal insulating layer 500, but is not limited thereto.
The coil part 200 may be embedded in the body 100 and exhibit characteristics of the coil component. For example, when the coil component 1000 is used as a power inductor, the coil part 200 may serve to stabilize a power source of an electronic device by storing an electric field as a magnetic field to maintain an output voltage.
The coil part 200 may include a first coil pattern 210, a second coil pattern 220, and a via (not illustrated).
The first and second coil patterns 210 and 220 and an internal insulating layer 500 to be described below may be formed to be sequentially stacked in the thickness (T) direction of the body 100.
Each of the first and second coil patterns 210 and 220 may be formed in a flat spiral shape. As an example, the first coil pattern 210 may form at least one turn on one surface of the internal insulating layer 500 centered on the thickness (T) direction of the body 100.
The via may penetrate through the internal insulating layer 500 so as to electrically connect the first and second coil patterns 210 and 220 to each other, thereby coming in contact with each of the first and second coil patterns 210 and 220. As a result, the coil part 200 applied to the present exemplary embodiment may be formed as a single coil generating a magnetic field in the thickness (T) direction of the body 100.
At least one of the first and second coil patterns 210 and 220 and the via may include at least one conductive layer.
As an example, when the second coil pattern 220 and the via are formed by plating, each of the second coil pattern 220 and the via may include a seed pattern SP of an electroless plating layer and a plating pattern of an electroplating layer. Here, the plating pattern of the electroplating layer may have a monolayer structure or a multilayer structure. The plating pattern having the multilayer structure may also be formed in a conformal film structure in which one plating pattern is covered with another plating pattern. Alternatively, the plating layer having the multilayer structure may also be formed so that only on one surface of one plating pattern, another plating pattern is stacked. The seed pattern SP of the second coil pattern 220 and the seed pattern of the via may be formed integrally with each other so that a boundary therebetween is not formed, but seed pattern SP of the second coil pattern 220 and the seed pattern of the via are not limited thereto. The plating pattern of the second coil pattern 220 and the plating pattern of the via may be formed integrally with each other so that a boundary therebetween is not formed, but the plating pattern of the second coil pattern 220 and the plating pattern of the via are not limited thereto.
As another example, when the coil part 200 is formed by separately forming the first and second coil patterns 210 and 220 and then collectively stacking the first and second coil patterns 210 and 220 on the internal insulating layer 500, the via may include a high-melting point metal layer and a low-melting point metal layer having a melting point lower than that of the high-melting point metal layer. Here, the low-melting point metal layer may be formed of solder containing lead (Pb) and/or tin (Sn). The low-melting point metal layer may be at least partially melted by a pressure and a temperature at the time of collective stacking, such that an inter-metallic compound (IMC) layer may be formed in a boundary between the low-melting point metal layer and the second coil pattern 220.
As an example, the first and second coil patterns 210 and 20 may be formed to protrude on lower and upper surfaces of the internal insulating layer 500, respectively. As another example, the first coil pattern 210 may be embedded in the lower surface of the internal insulating layer 500 so that a lower surface thereof is exposed to the lower surface of the internal insulating layer 500, and the second coil pattern 220 may be formed to protrude on the upper surface of the internal insulating layer 500. In this case, a concave portion may be formed in the lower surface of the first coil pattern 210, such that the lower surface of the internal insulating layer 500 and the lower surface of the first coil pattern 210 may not be positioned on the same plane. As another example, the first coil pattern 210 may be embedded in the lower surface of the internal insulating layer 500 so that the lower surface thereof is exposed to the lower surface of the internal insulating layer 500, and the second coil pattern 220 may be embedded in the upper surface of the internal insulating layer 500 so that an upper surface thereof is exposed to the upper surface of the internal insulating layer 500.
The first and second coil patterns 210 and 220 may be connected to the lead patterns 211 and 221 exposed to the first and second surfaces of the body 100, respectively. That is, the end portion of the first coil pattern 210 may be connected to a first lead pattern 211 exposed to the first surface of the body 100, and the end portion of the second coil pattern 220 may be connected to a second lead pattern 221 exposed to the second surface of the body 100. Since the first lead pattern 211 comes in contact with a first external electrode 300 to be described below, the first coil pattern 210 and the first external electrode 300 may be electrically connected to each other. Since the second lead pattern 221 comes in contact with a second external electrode 400 to be described below, the second coil pattern 220 and the second external electrode 400 may be electrically connected to each other.
The lead patterns 211 and 221 may be formed to entirely have a thickness smaller than that of the coil patterns 210 and 220 or formed to at least partially have a thickness smaller than that of the coil patterns 210 and 220, respectively. The portions of the lead pattern 211 and 221 having a thickness smaller than that of the coil patterns 210 and 220 may be disposed adjacent to the first and second external electrodes 300 and 400, and may be in direct contact with the first and second external electrodes 300 and 400.
As an example, as illustrated in FIG. 2, groove portions may be formed on some regions of the lead patterns 211 and 221 so that some portions of the lead patterns 211 and 221 at least partially have a smaller thickness than that of the coil patterns 210 and 220. For example, some portions of the lead patterns 211 and 221 may have a thickness less than or equal to 0.6× the thickness of the coil patterns 210 and 220.
Since the lead patterns 211 and 221 are formed to at least partially have a thickness smaller than that of the coil patterns 210 and 220, binding force between the magnetic composite sheet 100 and the coil part may be improved. Therefore, binding force between the coil part 200 and the body 100 may be improved. Further, since the lead patterns 211 and 221 are formed to at least partially have a thickness smaller than that of the coil patterns 210 and 220, a total amount of a magnetic material in the same volume may be increased as compared to a case in which the groove portions are not formed in the lead patterns 211 and 221. Therefore, a quality (Q) factor of the coil component 1000 may be improved.
The coil patterns 210 and 220, the lead patterns 211 and 221, and the via may each be formed of a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof, but are not limited thereto.
The internal insulating layer 500 may be formed of an insulating material including at least one of thermosetting insulating resins such as an epoxy resin, thermoplastic insulating resins such as polyimide, and photosensitive insulating resins, or an insulating material in which a reinforcing material such as glass fiber or an inorganic filler is impregnated in this insulating resin. As an example, the internal insulating layer 500 may be formed of an insulating material such as prepreg, an Ajinomoto build-up film (ABF), FR-4, a bismaleimide triazine resin, a photoimageable dielectric (PID), or the like, but is not limited thereto.
As the inorganic filler, at least one selected from the group consisting of silica (SiO2), alumina (Al2O3), silicon carbide (SiC), barium sulfate (BaSO4), talc, mud, mica powder, aluminum hydroxide (AlOH3), magnesium hydroxide (Mg(OH)2), calcium carbonate (CaCO3), magnesium carbonate (MgCO3), magnesium oxide (MgO), boron nitride (BN), aluminum borate (AlBO3), barium titanate (BaTiO3), and calcium zirconate (CaZrO3) may be used.
When the internal insulating layer 500 is formed of an insulating material containing a reinforcing material, the internal insulating layer 500 may provide more excellent rigidity. When the internal insulating layer 500 is formed of an insulating material that does not contain glass fiber, the internal insulating layer 500 is advantageous for thinning a thickness of the entire coil part 200. When the internal insulating layer 500 is formed of an insulating material containing a photosensitive insulating resin, the number of processes may be decreased, which is advantageous for decreasing a manufacturing cost, and a fine hole may be formed.
The insulating film 600 may be formed along surfaces of the first coil pattern 210, the internal insulating layer 500, and the second coil pattern 220. The insulating film 600 may be formed in order to protect and insulate the respective coil patterns 210 and 220 and contain an insulating material known in the art such as parylene, or the like. Any insulating material may be contained in the insulating film 600 without particular limitation. The insulating film 600 may be formed by a method such as a vapor deposition method, but is not limited thereto. The insulating film 600 may be formed by stacking an insulation film on both surfaces of the internal insulating layer 500 on which the first and second coil patterns 210 and 220 are formed.
Meanwhile, although not illustrated, at least one of the first and second coil patterns 210 and 220 may be formed in plural. As an example, the coil part 200 may have a structure in which a plurality of first coil patterns 210 are formed, and another first coil pattern is stacked on a lower surface of one first coil pattern. In this case, an additional insulating layer may be disposed between the plurality of first coil patterns 210, and the plurality of first coil patterns 210 may be connected to each other by a connection via penetrating through the additional insulating layer, but the first coil pattern 210 is not limited thereto.
The external electrodes 300 and 400 may be disposed on one surface of the body 100 and connected to the coil patterns 210 and 220. The external electrodes 300 and 400 may include a first external electrode 300 connected to the first coil pattern 210 and a second external electrode 400 connected to the second coil pattern 220. More specifically, the first external electrode 300 may include a first connection portion disposed on the first surface of the body 100 and connected to the first lead pattern 211 of the first coil pattern 211 and a first extension portion extended from the first connection portion to the sixth surface of the body 100. The second external electrode 400 may include a second connection portion disposed on the second surface of the body 100 and connected to the second lead pattern 221 of the second coil pattern 220 and a second extension portion extended from the second connection portion to the sixth surface of the body 100. The first and second extension portions each disposed on the sixth surface of the body 100 may be spaced apart from each other so that the first and second external electrodes 300 and 400 do not come in contact with each other.
The external electrodes 300 and 400 may electrically connect the coil component 1000 to a printed circuit board, or the like, when the coil component 1000 according to the present exemplary embodiment is mounted on the printed circuit board, or the like. As an example, the coil component 1000 according to the present exemplary embodiment may be mounted on the printed circuit board so that the sixth surface of the body 100 faces an upper surface of the printed circuit board, and the extension portions of the external electrodes 300 and 400 disposed on the sixth surface of the body 100 and a connection portion of the printed circuit board may be electrically connected to each other by solder, or the like.
The external electrodes 300 and 400 may include conductive resin layers and conductive layers formed on the conductive resin layers, respectively. The conductive resin layer may be formed by printing a paste, or the like, and may contain one or more conductive metals selected from the group consisting of copper (Cu), nickel (Ni), and silver (Ag), and a thermosetting resin. The conductive layer may contain one or more selected from the group consisting of nickel (Ni), copper (Cu), and tin (Sn), and be formed, for example, by plating.
Meanwhile, in the above-mentioned exemplary embodiments in the present disclosure, a description is provided on the assumption that the external electrodes 300 and 400 applied to the present disclosure are “L”-shaped electrodes composed of the connection portions and the extension portions, but this is only for convenience of explanation. Therefore, shapes of the external electrodes 300 and 400 may be variously changed. As an example, the external electrodes 300 and 400 are not formed on the first and second surfaces of the body 100 but may be formed only the sixth surface of the body 100 to thereby be connected to the coil part 200 through a via electrode, or the like. As another example, the external electrodes 300 and 400 may be “”-shaped electrodes including connection portions respectively formed on the first and second surfaces of the body 100, extension portions extended from the connection portions and disposed on the sixth surface of the body, and band portions extended from the connection portions and disposed on the fifth surface of the body 100, respectively. As another example, the external electrodes 300 and 400 may be five-face electrodes including connection portions formed on the first and second surfaces of the body 100, extension portions extended from the connection portions and disposed on the sixth surface of the body, and band portions extended from the connection portions and disposed on the third to fifth surfaces of the body 100, respectively.
Manufacturing Method of Coil Component
FIGS. 3 through 9 are views sequentially illustrating a manufacturing method of the coil component according to an exemplary embodiment in the present disclosure.
Referring to FIGS. 3 through 9, the method of manufacturing the coil component according to the present exemplary embodiment in the present disclosure may include: forming a plating resist on an internal insulating layer; forming a coil pattern and a lead pattern connected to the coil pattern and at least partially having a thickness smaller than that of the coil pattern by plating; removing the plating resist; and stacking a magnetic sheet on the internal insulating layer to form a body. Here, the plating resist may include an opening pattern corresponding to the coil pattern and a hollow pattern corresponding to the lead pattern, being in communication with the opening pattern, and having an upper portion at least partially covered by a cover portion.
Although a case in which a process for forming a second coil pattern 220 and a second lead pattern 221 is performed only on an upper surface of an internal insulating layer 500 is illustrated in FIGS. 3 through 9, this case is illustrated by way of example for convenience of explanation. Therefore, it should be considered that although not illustrated in FIGS. 3 through 9, a process for forming the first coil pattern 210 and the first lead pattern 211 described above is equally performed on a lower surface of the internal insulating layer 500 in each step.
Further, although a case in which the process is performed in units of a single component size is illustrated in FIGS. 3 through 9, a process to be described below may also be performed in units of a panel or strip rather than units of the component.
First, referring to FIG. 3, a seed layer may be formed on the internal insulating layer.
As an example, a seed layer SL may be an electroless plating layer formed on an upper surface of the internal insulating layer 500. As another example, the seed layer SL may be a metal film formed on one surface of the internal insulating layer 500 and an electroless plating layer formed on the metal film. As another example, the seed layer SL may be a copper film formed on one surface of the internal insulating layer 500.
Next, referring to FIGS. 4 and 5, a plating resist may be formed on the internal insulating layer on which the seed layer is formed.
A plating resist 700, which is a material for forming the second coil pattern 220 and the second lead pattern 221 on the upper surface of the internal insulating layer, may be formed by stacking a material for forming a plating resist such as a dry film on the seed layer SL, and selectively performing exposure and development on the material for forming a plating resist.
The plating resist 700 may include an opening pattern 710 formed at a position corresponding to the second coil pattern 220 and a hollow pattern 720 formed at a position corresponding to the second lead pattern 221. The hollow pattern 720 may be in communication with the opening pattern 710 and be at least partially covered by a cover portion 730. The cover portion 730 extends parallel to the surface of the insulating substrate and is spaced apart from the insulating substrate 500.
An example of a formation method of the plating resist 700 including the opening pattern 710 and the hollow pattern 720 will be described.
First, a negative type dry film may be stacked on an entire surface of the seed layer SL. Next, a first exposure mask of which regions corresponding to the positions of the opening pattern 710 and the hollow pattern 720 are blocked and the other region is opened may be disposed on the dry film, and then the dry film may be subjected to primary exposure. Next, a second exposure mask of which the region corresponding to the position of the hollow pattern 720 is opened and the other region is blocked may be disposed on the dry film, and then the dry film may be subjected to secondary exposure. Finally, the dry film may be subjected to development, such that the plating resist 700 including the opening pattern 710 and the hallow pattern 720 may be formed.
Here, since one region of the dry film on which the opening pattern 710 will be formed is a region that is not exposed in the primary exposure and secondary exposure, when this region is subjected to development, this region may become the opening pattern 710. Further, the secondary exposure may be performed on another region of the dry film on which the hollow pattern 720 will be formed, but exposure energy may be adjusted so that light is transferred only to an upper portion of the dry film in a thickness direction. Therefore, when development is performed after the secondary exposure, the hollow pattern 720 on which the cover portion 730 that is cured in the secondary exposure and is not removed by development is formed may be formed. Primary exposure energy and secondary exposure energy may be 1700 mJ/cm2 and 150 mJ/cm2, respectively, but are not limited thereto. The primary exposure energy and the secondary exposure energy may be changed depending on a material and a thickness of the dry film.
Meanwhile, although a description is provided on the assumption that the dry film is the negative type dry film, this case is only an example. Therefore, a case of using a positive type dry film is not excluded in the scope of the present disclosure.
Next, referring to FIG. 6, the coil pattern and the lead pattern may be formed.
The second coil pattern 220 and the second lead pattern 221 may be formed by filling the opening pattern 710 and the hollow pattern 720 of the plating resist 700 with a conductive material, respectively. The second coil pattern 220 and the second lead pattern 221 may be formed by electroplating using the seed layer SL as a plating lead line. Here, the electroplating may be performed using an anisotropic plating solution, but is not limited thereto. When the electroplating is performed using an anisotropic plating solution, the second coil pattern 220 may be formed to have a relatively high aspect ratio.
As described above, since the upper portion of the hollow pattern 720 may be at least partially covered by the cover portion 730, the second lead pattern 221 may be formed to at least partially have a thickness smaller than that of the coil pattern 220.
Next, referring to FIGS. 7 and 8, after removing the plating resist, the seed layer may be selectively removed.
The plating resist 700 may be stripped from the seed layer SL using a stripper.
When the plating resist 700 is removed, the seed layer SL may be exposed to the outside, and a region of the seed layer SL that is not covered by the second coil pattern 220 and the second lead pattern 221 may be selectively removed, such that a seed pattern SP may be formed between the second coil pattern 220 and the second lead pattern 221 and the internal insulating layer 500.
The seed pattern SP may be formed by performing flash etching, or the like, on the seed layer SL, but is not limited thereto.
Next, referring to FIG. 9, a magnetic sheet may be stacked on the internal insulating layer.
A through hole may be formed in the internal insulating layer 500 by removing a central portion of the internal insulating layer 500 on which the second coil pattern 220 and the second lead pattern 221 are not formed.
A magnetic sheet 110 may be the above-mentioned magnetic composite sheet 110, but is not limited thereto.
Meanwhile, although a case in which one magnetic sheet 110 is stacked is illustrated in FIG. 9, this case is only an example. Therefore, the magnetic sheets 110 may be stacked in two or more layers on the internal insulating layer 500.
In this way, the body 100 and the coil part 200 illustrated in FIGS. 1 and 2 may be formed.
Further, although not illustrated in FIG. 9, before stacking the magnetic sheet 110 on the internal insulating layer 500 or forming the through hole in the internal insulating layer 500, the insulating film 600 illustrated in FIG. 2 may be formed along the surfaces of the coil patterns 210 and 220, the lead patterns 211 and 221, and the internal insulating layer 500.
Thereafter, although not illustrated, external electrodes 300 and 400 may be formed on first and second surfaces of the body 100, respectively.
Meanwhile, hereinabove, a description is provided on the assumption that the seed pattern SP is formed by selectively removing the seed layer SL after entire forming the seed layer SL on one surface of the internal insulating layer 500, but the seed pattern SP may be formed on one surface of the internal insulating layer 500 to correspond to the second coil pattern 220 and the second lead pattern 221 using a separate resist pattern before forming the plating resist 700.
As set forth above, according to exemplary embodiments in the present disclosure, the coil component in which binding force between the body and the coil part is improved by forming the lead pattern to at least partially have a thickness smaller than that of the coil pattern may be provided.
While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present invention as defined by the appended claims.
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16213893
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samsung electro-mechanics co., ltd.
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USA
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B2
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Utility Patent Grant (with pre-grant publication) issued on or after January 2, 2001.
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Open
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Apr 27th, 2022 09:11AM
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Apr 27th, 2022 09:11AM
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Samsung
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krx:005930
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Samsung
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Apr 26th, 2022 12:00AM
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Dec 2nd, 2020 12:00AM
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https://www.uspto.gov?id=US11316251-20220426
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Radio frequency package
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A radio frequency package includes a first connection member having a first stack structure including at least one first insulating layer and at least one first wiring layer; a second connection member having a second stack structure including at least one second insulating layer and at least one second wiring layer; a core member including a core insulating layer and disposed between the first and second connection members; and a first chip antenna disposed to be surrounded by the core insulating layer. The first chip antenna includes a first dielectric layer disposed to be surrounded by the core insulating layer; a patch antenna pattern disposed on an upper surface of the first dielectric layer; and a feed via disposed to at least partially penetrate the first dielectric layer, providing a feed path of the patch antenna pattern and connected to the at least one first wiring layer.
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11316251
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1. A radio frequency package, comprising:
a first connection member having a first stack structure in which at least one first insulating layer and at least one first wiring layer are alternately stacked;
a second connection member having a second stack structure in which at least one second insulating layer and at least one second wiring layer are alternately stacked;
a core member comprising a core insulating layer and disposed between the first and second connection members; and
a first chip antenna disposed to be surrounded by the core insulating layer,
wherein the first chip antenna comprises:
a first dielectric layer disposed to be surrounded by the core insulating layer;
a patch antenna pattern disposed on an upper surface of the first dielectric layer; and
a feed via disposed to at least partially penetrate the first dielectric layer in a thickness direction of the radio frequency package, providing a feed path of the patch antenna pattern, and connected to the at least one first wiring layer.
2. The radio frequency package of claim 1, further comprising an electrical connection structure disposed on the first connection member to connect the feed via and the at least one first wiring layer,
wherein the electrical connection structure includes substantially the same material as the at least one first wiring layer.
3. The radio frequency package of claim 1, wherein an area of the second connection member, overlapping at least a portion of the patch antenna in the thickness direction, has an aperture shape.
4. The radio frequency package of claim 1, wherein the second connection member further comprises a solder resist (SR) layer disposed on an upper surface of the second stack structure,
wherein the SR layer further comprises a hole overlapping at least a portion of the patch antenna pattern in the thickness direction.
5. The radio frequency package of claim 1, wherein the at least one second wiring layer comprises a coupling patch pattern disposed to overlap the patch antenna pattern in the thickness direction.
6. The radio frequency package of claim 5, further comprising a connection via connecting the coupling patch pattern and the first chip antenna.
7. The radio frequency package of claim 1, further comprising a metal layer disposed on a side surface of the core insulating layer, facing the first chip antenna.
8. The radio frequency package of claim 1, further comprising an insulating member disposed in at least a portion of a space surrounded by the core insulating layer.
9. The radio frequency package of claim 1, wherein a thickness of the core insulating layer is greater than a thickness of one of the at least one first insulating layer and a thickness of one of the at least one second insulating layer.
10. The radio frequency package of claim 1, wherein the core member further comprises a core via penetrating the core insulating layer and connecting the at least one first wiring layer and the at least one second wiring layer.
11. The radio frequency package of claim 1, further comprising a second chip antenna disposed on an upper surface of the second connection member and connecting the at least one second wiring layer.
12. The radio frequency package of claim 11, wherein a size of a patch antenna pattern of the second chip antenna and a size of the patch antenna pattern of the first chip antenna are different from each other.
13. The radio frequency package of claim 11, wherein a dielectric layer of the second chip antenna and a dielectric layer of the first chip antenna have different dielectric constants.
14. The radio frequency package of claim 1, further comprising an impedance component disposed on an upper surface of the second connection member and connected to the at least one second wiring layer.
15. The radio frequency package of claim 1, further comprising a connector disposed on an upper surface of the second connection member and connected to the at least one second wiring layer.
16. The radio frequency package of claim 1, further comprising:
a radio frequency integrated circuit (RFIC) disposed on a lower surface of the first connection member; and
a sub-substrate disposed on the lower surface of the first connection member and surrounding the RFIC.
17. The radio frequency package of claim 1, wherein the first dielectric layer has a higher dielectric constant than the core insulating layer.
18. The radio frequency package of claim 1, wherein the first chip antenna further comprises a second dielectric layer disposed on an upper surface of the patch antenna pattern and surrounded by the core insulating layer.
19. The radio frequency package of claim 18, wherein:
the at least one second wiring layer comprises a coupling patch pattern disposed to overlap the patch antenna pattern in the thickness direction, and
the first chip antenna further comprises an upper patch pattern disposed on an upper surface of the second dielectric layer between the coupling patch pattern and the patch antenna pattern.
20. The radio frequency package of claim 18, wherein the first chip antenna further comprises an adhesive layer disposed between the first and second dielectric layers and having higher adhesion as compared to the first and second dielectric layers.
21. The radio frequency package of claim 20, wherein the adhesive layer has an air cavity in which the patch antenna pattern is disposed.
22. The radio frequency package of claim 1, wherein a side of the patch antenna pattern is oblique with respect to an external side surface of the core insulating layer.
23. A radio frequency package, comprising:
a core member comprising a core insulating layer in which a core via is disposed, and having a cavity penetrating at least a portion of the core insulating layer;
a chip antenna disposed in the cavity, wherein the chip antenna comprises a dielectric layer, a patch antenna pattern disposed on an upper surface of the dielectric layer, and a feed via penetrating the first dielectric layer and providing a feed path of the patch antenna pattern; and
a connection member disposed on one side of the core member and including a wiring layer connected to the core via and the feed via.
24. The radio frequency package of claim 23, further comprising:
a first via extending from the wiring layer towards the core member to connect to the core via; and
a second via extending from the wiring layer towards the chip antenna to connect to the feed via.
25. The radio frequency package of claim 24, further comprising
a core wiring layer disposed on the core insulating layer and between the core via and the first via, and connecting the core via and the first via to each other; and
an electrical connection structure disposed on the dielectric layer and between the feed via and the second via, and connecting the feed via and the second via to each other.
26. The radio frequency package of claim 23, further comprising a metal layer disposed on a side surface of the core insulating layer, facing the chip antenna.
27. The radio frequency package of claim 23, further comprising an insulating member disposed in at least a portion of the cavity.
28. A radio frequency package, comprising:
a core member comprising a core insulating layer and having a cavity penetrating at least a portion of the core insulating layer;
a chip antenna disposed in the cavity, wherein the chip antenna comprises a dielectric layer, a patch antenna pattern disposed on an upper surface of the dielectric layer, and a feed via penetrating the first dielectric layer and providing a feed path of the patch antenna pattern;
an insulating member covering the core member and the chip antenna and disposed in at least a portion of the cavity; and
a connection member including a wiring layer disposed on the insulating member,
wherein the wiring layer includes a coupling patch pattern overlapping the patch antenna pattern.
29. The radio frequency package of claim 28, further comprising a connection via connecting the coupling patch pattern and the chip antenna.
30. The radio frequency package of claim 28, wherein the connection member includes an aperture exposing at least a portion of the coupling patch pattern.
31. The radio frequency package of claim 28, further comprising a metal layer disposed on a side surface of the core insulating layer, facing the chip antenna.
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31
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CROSS-REFERENCE TO RELATED APPLICATION
This application claims the benefit under 35 U.S.C. § 119(a) of Korean Patent Application No. 10-2020-0083974 filed on Jul. 8, 2020, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.
TECHNICAL FIELD
The present disclosure relates to a radio frequency package.
BACKGROUND
Mobile communications data traffic has increased on an annual basis. Various techniques have been actively developed to support rapidly increasing data transmissions in wireless networks in real time. For example, conversion of Internet of Things (IoT)-based data into contents, augmented reality (AR), virtual reality (VR), live VR/AR linked with SNS, an automatic driving function, applications such as a sync view (transmission of real-time images from a user's viewpoint using a compact camera), and the like, may require communications (e.g., 5G communications, mmWave communications, and the like) which support the transmission and reception of large volumes of data.
Accordingly, there has been a large amount of research into mmWave communications including 5th generation (5G), and research into the commercialization and standardization of an antenna apparatus for implementing such communications has been increasingly conducted.
An RF signal within a high frequency band (e.g., 24 GHz, 28 GHz, 36 GHz, 39 GHz, 60 GHz, and the like) may be easily absorbed and lost while being transferred, such that communications quality may be degraded. Thus, an antenna for communications, based on a high frequency band, may need a technical approach different from that of a general antenna technique, and development of a special technique such as securing of antenna gain, integration between an antenna and an RFIC, securing of effective isotropic radiated power (EIRP), and the like, may be required.
SUMMARY
The present disclosure relates to a radio frequency package.
According to an aspect of the present disclosure, a radio frequency package may include a first connection member having a first stack structure in which at least one first insulating layer and at least one first wiring layer are alternately stacked; a second connection member having a second stack structure in which at least one second insulating layer and at least one second wiring layer are alternately stacked; a core member including a core insulating layer and disposed between the first and second connection members; and a first chip antenna disposed to be surrounded by the core insulating layer. The first chip antenna may include a first dielectric layer disposed to be surrounded by the core insulating layer; a patch antenna pattern disposed on an upper surface of the first dielectric layer; and a feed via disposed to at least partially penetrate the first dielectric layer in a thickness direction of the radio frequency package, providing a feed path of the patch antenna pattern and connected to the at least one first wiring layer.
According to an aspect of the present disclosure, a radio frequency package may include a core member including a core insulating layer in which a core via is disposed, and having a cavity penetrating at least a portion of the core insulating layer; a chip antenna disposed in the cavity, wherein the chip antenna includes a dielectric layer, a patch antenna pattern disposed on an upper surface of the dielectric layer, and a feed via penetrating the first dielectric layer and providing a feed path of the patch antenna pattern; and a connection member disposed on one side of the core member and including a wiring layer connected to the core via and the feed via.
According to an aspect of the present disclosure, a radio frequency package may include a core member including a core insulating layer and having a cavity penetrating at least a portion of the core insulating layer; a chip antenna disposed in the cavity, wherein the chip antenna includes a dielectric layer, a patch antenna pattern disposed on an upper surface of the dielectric layer, and a feed via penetrating the first dielectric layer and providing a feed path of the patch antenna pattern; an insulating member covering the core member and the chip antenna and disposed in at least a portion of the cavity; and a connection member including a wiring layer disposed on the insulating member. The wiring layer includes a coupling patch pattern overlapping the patch antenna pattern.
BRIEF DESCRIPTION OF DRAWINGS
FIGS. 1A to 1C are diagrams illustrating a radio frequency package according to an example embodiment.
FIGS. 2A to 2D are diagrams illustrating various structures of a chip antenna of a radio frequency package according to an example embodiment.
FIGS. 3A and 3B are diagrams illustrating a connection structure of a second connection member of a radio frequency package according to an example embodiment.
FIGS. 4A and 4B are diagrams illustrating an upper surface of a structure of a radio frequency package according to an example embodiment, in which a second connection member is omitted.
FIGS. 5A to 5F are diagrams illustrating a method for manufacturing a radio frequency package according to an example embodiment.
FIGS. 6A and 6B are diagrams illustrating a connection structure of a first connection member of a radio frequency package according to an example embodiment.
FIG. 7 is a planar view exemplifying a disposition of a substrate in an electronic device, in which a chip antenna according to an example embodiment is disposed.
DETAILED DESCRIPTION
The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent after an understanding of the disclosure of this application. For example, the sequences of operations described herein are merely examples, and are not limited to those set forth herein, but may be changed as will be apparent after an understanding of the disclosure of this application, with the exception of operations necessarily occurring in a certain order. Further, descriptions of features that are known in the art may be omitted for increased clarity and conciseness. Accordingly, the features described herein may be embodied in different forms, and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided merely to illustrate some of the many possible ways of implementing the methods, apparatuses, and/or systems described herein that will be apparent after an understanding of the disclosure of this application.
Hereinbelow, the example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, such that one of ordinary skill in the art could easily practice the invention.
FIGS. 1A to 1C are diagrams illustrating a radio frequency package according to an example embodiment.
Referring to FIG. 1A, a radio frequency package 200a, according to an example embodiment, may have a structure in which a first chip antenna 100a is disposed, and the first chip antenna 100a may include a first dielectric layer 131a, a patch antenna pattern 110a and a feed via 120a.
The first dielectric layer 131a may have a dielectric medium having a higher dielectric constant than air. For example, the first dielectric layer 131a may be formed of ceramic and may thus have a comparatively high dielectric constant.
The first chip antenna 100a may be manufactured separately from the remaining structure of the radio frequency package 200a and is disposed in the radio frequency package 200a. In this regard, the first dielectric layer 131a may be formed of a material different from a material (e.g., prepreg) of an insulating layer of the radio frequency package 200a and may be implemented in a method selected among various and released methods as compared to the insulating layer.
In this regard, the first chip antenna 100a may have further improved antenna performance (e.g., gain, bandwidth, maximum output and polarization efficiency) for a size thereof, as compared to an antenna based on a structure in which an insulating layer and a wiring layer of a connection member are stacked.
For example, the first dielectric layer 131a may be formed of a ceramic-based material, such as low temperature co-fired ceramic (LTCC), a glass-based material having a comparatively high dielectric constant or a material, such as Teflon, having a comparatively low dissipation factor. Alternately, the first dielectric layer 131a may be configured to have a higher dielectric constant or greater durability by containing at least one of magnesium (Mg), silicon (Si), aluminum (Al), calcium (Ca) or titanium (Ti). For example, the first dielectric layer 131a may contain Mg2SiO4, MgAlO4 or CaTiO3.
As the first dielectric layer 131a has a higher dielectric constant, a wavelength of a radio frequency transmitted or propagated may be reduced. The shorter the wavelength of an RF signal is, the smaller the size of the first dielectric layer 131a is. A size of the first chip antenna 100a, according to an example embodiment, may be reduced. The lower the dissipation factor of the first dielectric layer 131a is, the smaller the energy loss of the RF signal is in the first dielectric layer 131a.
As the size of the first chip antenna 100a is reduced, the number of the first chip antenna 100a arrangeable in a unit volume may increase. As the number of the first chip antenna 100a arrangeable in a unit volume increases, a total gain or a maximum output of a plurality of the first chip antennas 100a may increase.
Accordingly, as the first dielectric layer 131a has a higher dielectric constant, performance of the first chip antenna 100a may effectively increase for a size thereof.
The patch antenna pattern 110a may be disposed on an upper surface of the first dielectric layer 131a. A comparatively large upper surface of the patch antenna pattern 110a may allow a radiation pattern to be concentrated in a vertical direction (e.g., z direction) and can thus remotely transmit and/or receive an RF signal in a vertical direction. Further, an RF signal having a frequency (e.g., 24 GHz, 28 GHz, 36 GHz, 39 GHz, 60 GHz) within a bandwidth based on a resonance frequency may be transmitted and/or received.
For example, the patch antenna pattern 110a may be formed by drying a conductive paste while being applied and/or charged on the first dielectric layer 131a.
The feed via 120a may be disposed to at least partially penetrate the first dielectric layer 131a in a thickness direction and may also function as a feed path of the patch antenna pattern 110a. That is, the feed via 120a may provide a path for a surface current flowing in the patch antenna pattern 110a when the patch antenna pattern 110a remotely transmits and/or receives an RF signal.
For example, the feed via 120a may have a structure which extends in a vertical direction within the first dielectric layer 131a and may be formed through a process in which a conductive material (e.g., copper, nickel, tin, silver, gold, palladium, and the like) is filled in a through hole formed in the first dielectric layer 131a by a laser.
For example, the feed via 120a may be in contact with one point of the patch antenna pattern 110a, and may also provide a feed path to the patch antenna pattern 110 without being in contact with the patch antenna pattern 110a depending on a design.
Referring to FIG. 1A, a radio frequency package 200a, according to an example embodiment, may include a first connection member 210a, a second connection member 220a and a core member 230a.
The first connection member 210a may have a first stack structure in which at least one first insulating layer 211a and at least one first wiring layer 212a are alternately stacked. For example, the first connection member 210a may include a first via 213a extending in a direction perpendicular to the first insulating layer 211a and may further include a first SR (solder resist) layer 214a.
For example, the first connection member 210a may have a structure of being built up downwardly of the core member 230a. Accordingly, the first via 213a which may be included in the first connection member 210a may have a structure in which a lower portion has a greater width than an upper portion.
The second connection member 220a may have a second stack structure in which at least one second insulating layer 221a and at least one second wiring layer 222a are alternately stacked. For example, the second connection member 220a may have a second via 223a extending in a direction perpendicular to the second insulating layer 221a and may further include a second SR layer 224a.
For example, the second connection member 220a may have a structure of being built up upwardly of the core member 230a. Accordingly, the second via 223a which may be included in the second connection member 220a may have a structure in which an upper portion has a greater width than a lower portion.
The at least one first wiring layer 212a and the at least one second wiring layer 222a may be formed in at least a portion of an upper surface of a lower surface of an insulating layer corresponding to include a separately designed wire and/or plane. The wire and/or plane may be electrically connected to the first via 213a and/or the second via 223a.
For example, the at least one first wiring layer 212a, the at least one second wiring layer 222a, the first via 213a and the second via 223a may be formed of a metal material (e.g., at least one conductive material of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or alloys thereof).
For example, the at least one first insulating layer 211a, the at least one second insulating layer 221a and the core insulating layer 231a may be implemented as a thermosetting resin such as FR4, liquid crystal polymer (LCP), low temperature co-fired ceramic (LTCC), and an epoxy resin, a thermoplastic resin such as polyimide, a resin in which the thermosetting or thermoplastic resin is impregnated with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), prepreg, Ajinomoto build-up film (ABF), FR-4, bismaleimide triazine (BT), a photoimagable dielectric (PID) resin, a copper clad laminate (CCL), or a glass or ceramic-based insulating material.
The core member 230a may include the core insulating layer 231a and may be disposed between the first and second connection members 210a and 220a. For example, the core member 230a may include a core wiring layer 232a disposed on an upper surface and/or a lower surface of the core insulating layer 231a and may include a core via 233a penetrating the core insulating layer 231a and electrically connecting the at least one first wiring layer 212a and the at least one second wiring layer 222a.
The core insulating layer 231a may surround the first chip antenna 100a. For example, the core insulating layer 231a may include a through hole or a cavity, and the first chip antenna 100a may be surrounded by the core insulating layer 231 by being disposed inside the through hole or the cavity. The first dielectric layer 131a may also be surrounded by the core insulating layer 231a.
In this regard, the radio frequency package 200a, according to an example embodiment, can effectively provide a dispositional space of the first chip antenna 100a while employing the first chip antenna 100a capable of having comparatively improved antenna performance (e.g., gain, bandwidth, maximum output and polarization efficiency) for a size thereof.
For example, the radio frequency package 200a, according to an example embodiment, may use the first chip antenna 100a without using a mounting space on an upper and/or lower surface and can thus have a further reduced surface area in a horizontal direction. A larger number of components (e.g., impedance component, radio frequency filter, and the like) requiring a mounting space on an upper and/or lower surface may be used more freely.
Further, as the first and second connection members 210a and 220a can press the core insulating layer 231 therebetween and the first chip antenna 100a together, the radio frequency package 200a, according to an example embodiment, can secure structural stability (e.g., frequency of warpage occurrence, strength) while employing the first chip antenna 100a.
In addition, the first chip antenna 100a can be electrically connected to the first wiring layer 212a without a solder having an unstable shape and a relatively low melting point. In this regard, energy loss of a remotely transmitted/received RF signal when passing between the first connection member 210a and the first chip antenna 100a may be reduced.
For example, the first chip antenna 100a may further include an electrical connection structure 160a connecting the feed via 120a and the at least one first wiring layer 212a on the first connection member 210a.
The electrical connection structure 160a may be formed of the same material (e.g., copper) as the at least one first wiring layer 212a and may be disposed before the first chip antenna 100a is built in the radio frequency package 200a and can thus have a more stable shape. Accordingly, the RF signal, which is remotely transmitted/received, may have further reduced energy loss when passing between the first connection member 210a and the first chip antenna 100a.
Referring to FIG. 1A, the at least one second wiring layer 222a may include a coupling patch pattern 225a disposed to overlap the patch antenna pattern 110 in a vertical direction. In one example, the vertical direction may refer to a direction in which insulating layers and wiring layers are stacked.
The coupling patch pattern 225a may be electromagnetically coupled with the patch antenna pattern 110a and may provide an additional resonance frequency to the patch antenna pattern 110a. Accordingly, the patch antenna pattern 110a may have a further greater bandwidth.
As the coupling patch pattern 225a is spaced apparat from the first chip antenna 100a and is disposed in the second connection member 220a, the first chip antenna 100a may have an extended bandwidth based on the coupling patch pattern 225a without having an increased thickness thereof in the vertical direction.
Referring to FIG. 1A, the core member 230a may further include a plating member 235a such as a metal layer disposed on a side surface facing the first chip antenna 100a in the core insulating layer 231a.
As the plating member 235a can reflect a horizontal component, among horizontal and vertical components included in a radiated RF signal, a radiation pattern of the first chip antenna 100a may be further concentrated in the vertical direction (e.g., z direction), and gain of the first chip antenna 100a may be further improved.
For example, the plating member 235a may be formed after a through hole or a cavity is formed in the core insulating layer 231a and before the first chip antenna 100a is disposed.
Referring to FIG. 1A, the core member 230a may further include an insulating member 240a disposed to fill at least a portion of the space (e.g., through hole, cavity) surrounded by the core insulating layer 231a.
In this regard, structural stability of the core member 230a may be further improved, and accordingly, the radio frequency package 200a, according to an example embodiment, can secure structural stability (e.g., frequency of warpage occurrence, strength) while employing the first chip antenna 100a.
Further, the insulating member 240a can support build-up of the first and second connection members 210a and 220a and can thus support structural stability thereof.
Referring to FIG. 1B, a radio frequency package 200b according to an example embodiment may have a structure in which the coupling patch pattern 225a and/or the plating member 235a illustrated in FIG. 1A are omitted and can effectively provide a dispositional space of the first chip antenna 100a while employing the first chip antenna 100a capable of comparatively having further improved antenna performance for a size thereof.
Referring to FIG. 1C, a radio frequency package 200c according to an example embodiment may have a structure in which the core via 233a illustrated in FIG. 1B is further omitted.
Meanwhile, a thickness H3 of the core insulating layer 231a may be greater than a thickness H1 of the at least one first insulating layer and a thickness H2 of the at least one second insulating layer. Accordingly, the radio frequency package 200c according to an example embodiment can have further improved structural stability (e.g., frequency of warpage occurrence, strength) while employing the first chip antenna 100a.
FIGS. 2A to 2D are diagrams illustrating various structures of a chip antenna of a radio frequency package according to an example embodiment.
Referring to FIG. 2A, a first chip antenna 100d of a radio frequency package 200d according to an example embodiment may further include at least one of a second dielectric layer 132b, an adhesive layer 140b and an upper patch pattern 112b.
The second dielectric layer 132b may be disposed on an upper surface of a patch antenna pattern 110b and may be surrounded by a core insulating layer 231a. For example, the second dielectric layer 132b may be implemented in the same manner as the first dielectric layer 131b and may be formed of the same material.
The second dielectric layer 132b may be formed of a material different from that of the core insulating layer 231a of the radio frequency package 200d and may be implemented in a manner selected among various and free manners as compared to the core insulating layer 231a.
For example, the second dielectric layer 132b may act as a dielectric medium having a relatively high dielectric constant or a relatively low dissipation factor and can further concentrate a radiation pattern of the patch antenna pattern 131b in a vertical direction (e.g., z direction). The second dielectric layer 132b may further increase gain of the patch antenna pattern 131b.
The adhesive layer 140b may be disposed between first and second dielectric layers 131b and 132b and may have stronger adhesion as compared to the first and second dielectric layers 131b and 132b. For example, the adhesive layer 140b may be formed of an adhesive polymer.
In this regard, a positional relationship between the first and second dielectric layers 131b and 132b may be fixed more stably, and accordingly, a dielectric medium boundary condition of the first and second dielectric layers 131b and 132b can more effectively concentrate the radiation pattern of the patch antenna pattern 131b in a vertical direction (e.g., z direction).
An upper patch pattern 112b may be disposed on an upper surface of the second dielectric layer 132b between a coupling patch pattern 225a and the patch antenna pattern 110b.
For example, the upper patch pattern 112b may be electromagnetically coupled to the patch antenna pattern 110b and may provide an additional resonance frequency to the patch antenna pattern 110. In this regard, the patch antenna pattern 110b may have a further greater bandwidth.
For example, the upper patch pattern 112b may have a horizontal size different from that of the patch antenna pattern 110b and may have a second bandwidth, not overlapping a first bandwidth of the patch antenna pattern 110b.
In this regard, the first chip antenna 100b may have a plurality of frequency bandwidths and may transmit and/or receive first and second RF signals having different fundamental frequencies.
Referring to FIG. 2B, a first chip antenna 100c of a radio frequency 200e according to an example embodiment may include a feed via 120a providing a feed path of a first RF signal and a feed via 120c providing a feed path of a second RF signal.
The radio frequency 200e may further include a connection via 226b electrically connecting a coupling patch pattern 225b and a first chip antenna 100c.
For example, the connection via 226b may provide the feed path of the second RF signal to the coupling patch pattern 225b and may be electrically connected to the feed via 120c.
A structure in which the connection via 226b and the feed via 120c are connected may penetrate the patch antenna pattern 110a and may not be in contact with the patch antenna pattern 110a.
Referring to FIG. 2C, an adhesive layer 140c of a first chip antenna 100d of a radio frequency 200f according to an example embodiment may have an air cavity 141b in which the patch antenna pattern 110b is disposed.
The air cavity 141b may include air having a lower dielectric constant than the adhesive layer 140c and may act as a dielectric medium having a relatively low dielectric constant. In this regard, energy leaking in a horizontal direction in an electromagnetic coupling process for a coupling patch pattern 225b and/or an upper patch pattern 112b of the patch antenna pattern 110a may be reduced. Accordingly, antenna performance of the first chip antenna 100d may be further improved.
Referring to FIG. 2D, a second connection member 220a of a radio frequency 200g according to an example embodiment may have a region 228a overlapping at least a portion of a patch antenna pattern 110a in the form of an aperture.
In this regard, a dielectric medium boundary condition may be formed on a side surface of a region 228a. By refracting and/or reflecting a horizontal component of an RF signal remotely transmitted/received to/from the patch antenna pattern 110a, a radiation pattern of the patch antenna pattern 110a may be further concentrated in a vertical direction (e.g., z direction), and gain of the patch antenna pattern 110a may be further improved.
For example, a second SR layer 224a may have a hole formed in the region 228a overlapping at least a portion of the patch antenna pattern 110a.
In this regard, a height of the aperture of the region 228a of the second connection member 220a may be increased without an increase in a substantial thickness of the radio frequency package 200g. As such, the gain of the patch antenna pattern 110a may be further improved for the thickness of the radio frequency package 200g.
FIGS. 3A and 3B are diagrams illustrating a connection structure of a second connection member of a radio frequency package according to an example embodiment.
Referring to FIG. 3A, a radio frequency package 200h according to an example embodiment may further include an impedance component 350 disposed on an upper surface of a second connection member 220a and electrically connected to at least one second wiring layer 222a.
For example, the impedance component 350 may be a capacitor or an inductor and may include an impedance main body 351 forming impedance and an external electrode 352 delivering the impedance.
The external electrode 352 may be mounted on an upper surface of the second connection member 220a through a mounting-electrical connection structure 331. The mounting-electrical connection structure 331 may couple the second connection member 220a to the impedance component 350 based on a solder having a relatively low melting point and may be inserted into a predetermined location of the second SR layer 224a.
The impedance component 350 can deliver impedance to an outside (e.g., RFIC) through the external electrode 352 and the at least one second wiring layer 222a and the core via and the at least one first wiring layer 212a.
The radio frequency package 200h according to an example embodiment may further include a connector 340 disposed on an upper surface of the second connection member 220a and electrically connected to the at least one second wiring layer 222a.
The connector 340 may provide an electric path of a base signal of a frequency lower than that of an RF signal remotely transmitted/received through the first chi antenna 100a. The base signal can be delivered to an outside (e.g., RFIC) through the connector 340 and the at least one second wiring layer 222a and the core via 233a and the at least one first wiring layer 212a. The base signal may also be converted into an RF signal in the outside (e.g., RFIC), and the RF signal may be delivered to the first chip antenna 100a through the at least one first wiring layer 212a to be radiated.
For example, the connector 340 may have a structure in which a coaxial cable is physically connected thereto, but is not limited thereto.
Referring to FIG. 3B, a radio frequency package 200i according to an example embodiment may further include second chip antennas 400a and 400b disposed on an upper surface of the second connection member 220a and electrically connected to the at least one second wiring layer 222a.
The second chip antenna 400a may include at least a portion of a patch antenna pattern 410a, a feed via 420a, a dielectric layer 430a and an electrical connection structure 460a, and the second chip antenna 400b may include at least a portion of a patch antenna pattern 410b, a feed via 420b, a dielectric layer 430b and an electrical connection structure 460b.
The second chip antenna 400a and 400b may be manufactured in a similar or same manner as the first chip antenna 100a and may be mounted on an upper surface of the second connection member 220a through mounting-electrical connection structures 332a and 332b. The mounting-electrical connection structures 332a and 332b may be a solder ball or a pad, but are not limited thereto.
As a radiation pattern of the first chip antenna 100a and those of the second chip antennas 400a and 400b may overlap each other, the radio frequency package 200i according to an example embodiment may possess gain and maximum output corresponding to a total number of the first chip antenna 100a and the second chip antennas 400a and 400b.
As the first chip antenna 100a is built in the radio frequency package 200i, the total number of the first chip antenna 100a and the second chip antennas 400a and 400b may increase for a size of the radio frequency package 200i.
Accordingly, the radio frequency package 200i according to an example embodiment may have gain and large maximum output improved for the size thereof.
For example, sizes of the patch antenna patterns 410a and 410b of the second chip antennas 400a and 400b and that of the patch antenna pattern 110a of the first chip antenna 100a may be different from each other. For example, dielectric constants of the dielectric layers 430a and 430b of the second chip antennas 400a and 400b and that of the first dielectric layer 131a of the first chip antenna 100a may be different from each other.
That is, a first frequency bandwidth of the first chip antenna 100a and a second frequency bandwidth of the second chip antennas 400a and 400b may be different from each other, and the radio frequency package 200i according to an example embodiment may remotely transmit/receive first and second RF signals belonging to a plurality of frequency bandwidths which are different from each other.
As the first chip antenna 100a may be disposed in a lower portion than the second chip antennas 400a and 400b, electromagnetic interference therebetween may be reduced. In this regard, the radio frequency package 200i according to an example embodiment may improve overall gain of a plurality of different frequency bandwidths.
Furthermore, as the radio frequency package 200i according to an example embodiment can remotely transmit/receive the first and second RF signals belonging to a plurality of different frequency bandwidths while employing the first chip antenna 100a and the second chip antennas 400a and 400b implemented to be focused on a single frequency bandwidth, overall antenna performance (e.g., bandwidth, maximum output, polarization efficiency, and the like) of a plurality of different frequency bandwidths may be improved.
FIGS. 4A and 4B are diagrams illustrating an upper surface of a structure of a radio frequency package according to an example embodiment, in which a second connection member is omitted. The radio frequency package in FIG. 4A or FIG. 4B may correspond to one or more of the above-described radio frequency packages.
Referring to FIG. 4A, a radio frequency package 200k according to an example embodiment may include a plurality of first chip antennas 100k and may have a structure in which a plurality of the first chip antennas 100k are disposed in a plurality of through holes of a core insulating layer 231a.
For example, a patch antenna pattern 110c, a first dielectric layer 131c and a through hole may have a polygonal shape.
The patch antenna pattern 110c may be disposed to be oblique with respect to an external side surface of a variant core insulating layer 231a of the patch antenna pattern 110c. For example, the patch antenna pattern 110c may have a shape which is 45° rotated on an xy plane.
A surface current according to remote transmittance/receipt of an RF signal of the patch antenna pattern 110c may flow from one side to the other side, and an electric field corresponding to the surface current may flow in a direction the same as that of the surface current. A magnetic field corresponding to the surface current may flow in a direction perpendicular to that of the surface current.
When the patch antenna pattern 110c is disposed to be oblique with respect to an external side surface of a variant core insulating layer 231a of the patch antenna pattern 110c, the electric field and the magnetic field corresponding to the surface current may be formed to avoid a neighboring chip antenna and may thus have reduced electromagnetic interference provided to the neighboring chip antenna. Accordingly, overall gain of a plurality of the first chip antennas 100k may be improved.
Referring to FIG. 4B, a radio frequency package 200l according to an example embodiment may include a plurality of first chip antennas 100l, and a plurality of patch antenna patterns 110d and 110e of a plurality of the first chip antenna 100l may have a polygonal and/or circular shape.
For example, a plurality of the first chip antennas 100l may be manufactured by cutting a relatively large dielectric layer in a vertical direction while having a plurality of the patch antenna patterns 110d and 110e formed on the relatively large dielectric layer.
FIGS. 5A to 5F are diagrams illustrating a method for manufacturing a radio frequency package according to an example embodiment.
Referring to FIG. 5A, a radio frequency package in a first state 1201 may have a structure in which a copper clad 1239 is stacked on an upper surface and a lower surface of a core insulating layer 1231.
A radio frequency package in a second state 1202 may have a structure in which the copper clad is removed from the core insulating layer 1231 and a through hole and a via hole are formed.
A radio frequency package in a third state 1203 may have a structure in which a dry film 1238 is formed on an upper surface and a lower surface of the core insulating layer 1231.
Referring to FIG. 5B, a radio frequency package in a fourth state 1204 may have a structure in which a core via 1233 is formed in the via hole of the core insulating layer 1231, a core insulating layer 1232 is formed on an upper surface and/or a lower surface of the core insulating layer 1231 and a plating member 1235 is formed on an interface of the through hole of the core insulating layer 1231. The structure corresponds to the core member 1230 and may be a supporting base for build-up of first and second connection members 1210 and 1220.
A radio frequency package in a fifth state 1205 may have a structure in which a support film 1237 is disposed on a lower surface of the core member 1230.
A radio frequency package in a sixth state 1206 may have a structure in which a first chip antenna 1100 is disposed in the through hole of the core member 1230 and may be subject to a plasma cleaning process. The first chip antenna 1100, while being coupled to a patch antenna pattern 1110, a feed via 1120, a first dielectric layer 1131 and an electrical connection structure 1160, may be disposed on an upper surface of the support film 1237.
Referring to FIG. 5C, a radio frequency package in a seventh state 1207 may have a structure in which an insulating member 1240 is filled in the through hole of the core member 1230 and an upper surface of the core member 1230.
A radio frequency package in a eighth state 1208 may have a structure in which the support film 1237 is removed and may be subject to a plasma cleaning process.
A radio frequency package in a ninth state 1209 may have a structure in which the insulating member 1240 extends toward a lower surface of the core member 1230.
Referring to FIG. 5D, a radio frequency package in a tenth state 1210 may have a structure in which a via hole is formed on an upper surface and a lower surface of the insulating member 1240.
A radio frequency package in an eleventh state 1211 may have a structure in which first and second vias 1213 and 1223 are formed in the via hole of the insulating member 1240 and first and second wiring layers 1212 and 1222 are formed surfaces of the insulating member 1240 and may be subject to a surface treating process.
A radio frequency package in a twelfth state 1212 may have a structure in which a coupling patch pattern 1225 is formed on an upper surface of the insulating member 1240.
Referring to FIG. 5E, a radio frequency package in a thirteenth state 1213 may have a structure in which first and second insulating layers 1211 and 1221 are formed on an upper surface and a lower surface of the insulating member 1240.
A radio frequency package in a fourteenth state 1214 may have a structure in which a via hole is formed in the first and second insulating layers 1211 and 1221.
A radio frequency package in a fifteenth state 1215 may have a structure in which the first and second wiring layers 1212 and 1222 are formed on an upper surface and a lower surface of the first and second insulating layers 1211 and 1221.
Processes of the radio frequency packages in the thirteenth state 1213 to the fifteenth state 1215 may be repeated, and the number of the first and second insulating layers 1211 and 1221 and the first and second wiring layers 1212 and 1222, which are stacked, may be determined depending on the number of repeated processes.
Referring to FIG. 5F, a radio frequency package in a sixteenth state 1216 may have a structure in which a portion of the second insulating layer 1221, overlapping the coupling patch pattern 1225, is removed.
A radio frequency package in a seventeenth state 1217 may have a structure in which first and second SR layers 1214 and 1224 are formed and a portion 1228 of the second SR layer 1224, overlapping the coupling patch pattern 1225, may be removed. For example, the overlapped region 1228 may be removed by a method based on microparticle collision (e.g., a sandblast method) or a method based on laser radiation.
Although reference numerals different from those shown in FIGS. 1A-4B are shown in in FIGS. 5A-5F, the structures shown in FIGS. 1A-4B may be obtained based on the method shown in FIGS. 5A-5F or may be obtained based on the method shown in FIGS. 5A-5F with some modification.
FIGS. 6A and 6B are diagrams illustrating a connection structure of a first connection member of a radio frequency package according to an example embodiment.
Referring to FIG. 6A, a radio frequency package 200m according to an example embodiment may further include a radio frequency integrated circuit (RFIC) 310 and a sub-substrate 370.
The RFIC 310 may be disposed on a lower surface of a first connection member 210a and may be mounted via a mounting-electrical connection structure 333.
The RFIC 310 may signal-process an RF signal remotely transmitted/received to/from a first chip antenna 100a and a base signal of a frequency lower than that of the RF signal. For example, the signal-process may include frequency conversion, filtering, amplification and phase control.
The sub-substrate 370 may be disposed on a lower surface of the first connection member 210a and may surround the RFIC 310 and may be mounted via the mounting-electrical connection structure 334.
For example, the sub-substrate 370 may include a sub-insulating layer 371, a sub-wring layer 372 and a sub-via 373 and may act as a path for power supply or the base signal.
For example, at least a portion of a space in which the sub-substrate 370 surrounds the RFIC 310 may be filled with an encapsulant such as photoimageable encapsulant (PIE), Ajinomoto build-up film (ABF), an epoxy molding compound (EMC), and the like.
Referring to FIG. 6B, a radio frequency package 200n according to an example embodiment may be mounted on a base substrate 380 via a mounting-electrical connection structure 335. The base substrate 380 may be a printed circuit board and may include a transfer path of a base signal.
FIG. 7 is a planar view exemplifying a disposition of a substrate in an electronic device, in which a chip antenna according to an example embodiment is disposed.
Referring to FIG. 7, radio frequency packages 100a-1 and 100a-2, which may be implemented with one or more of the above-described radio frequency packages, may be respectively disposed adjacent to different edges of an electronic device 700.
The electronic device 700 may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game, a smart watch, an automotive component, or the like, but is not limited thereto.
The electronic device 700 may include a base substrate 600, and the base substrate 600 may further include a communication modem 610 and a baseband IC 620.
The communication modem 610 may include any one or any combination of any two or more of: a memory chip such as a volatile memory (e.g., a DRAM), a non-volatile memory (e.g., a ROM), a flash memory, or the like; an application processor chip such as a central processor (e.g., a CPU), a graphics processor (e.g., a GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like; and a logic chip such as an analog-to-digital converter, an application-specific integrated circuit (ASIC), or the like.
The baseband IC 620 may generate a base signal by performing analog-to-digital conversion, and amplification, filtering and frequency conversion on an analog signal. Abase signal input to and output from the baseband IC 620 may be transferred to the radio frequency packages 100a-1 and 100a-2 via a coaxial cable, and the coaxial cable may be electrically connected to an electrical connection structure of the radio frequency packages 100a-1 and 100a-2.
For example, a frequency of the base signal may be a baseband and may be a frequency (e.g., several GHzs) corresponding to an intermediate frequency (IF). A frequency (e.g., 28 GHz or 39 GHz) of an RF signal may be higher than the IF and may correspond to a millimeter wave (mmWave).
The RF signals described in the example embodiments may include protocols such as wireless fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, or the like), worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, or the like), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high speed packet access+ (HSPA+), high speed downlink packet access+ (HSDPA+), high speed uplink packet access+ (HSUPA+), enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G, 4G, and 5G protocols, and any other wireless and wired protocols designated after the above-mentioned protocols, but are not limited thereto.
According to the embodiments described herein, the radio frequency package can effectively provide a dispositional space of a chip antenna while employing a chip antenna capable of having comparatively improved antenna performance (e.g., gain, bandwidth, maximum output and polarization efficiency) for a size thereof.
One element described in a particular example embodiment, even if it is not described in another example embodiment, may be understood as a description related to another example embodiment, unless an opposite or contradictory description is provided therein.
While this disclosure includes specific examples, it will be apparent after an understanding of the disclosure of this application that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or replaced or supplemented by other components or their equivalents. In addition, respective embodiments may be combined with each other. For example, the pressing members disclosed in the above-described embodiments may be used in combination with each other in one force sensing device. Therefore, the scope of the disclosure is defined not by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.
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17109619
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samsung electro-mechanics co., ltd.
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USA
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B2
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Utility Patent Grant (with pre-grant publication) issued on or after January 2, 2001.
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Open
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Apr 27th, 2022 09:11AM
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Apr 27th, 2022 09:11AM
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Samsung
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